Bruce Jacob and Trevor Mudge. Software-managed address translation. In Proc. 3rd HPCA, pages 156--167, 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....order to obtain the base address. Any effective solution must avoid a cache lookup for an unknown base address (a range check) This can be achieved by associating the protection information with each I D cache line. Placing the actual protection bits in each cache line has been proposed before [42]. However this approach makes the protection bits global (i.e. independent of the protection context) which can only be avoided by either flushing the caches on a context switch, or adding a PDID tag to them. In addition, protection updates require that each cache line s permissions be updated in ....

Bruce Jacob and Trevor Mudge. Software-managed address translation. In Proc. 3rd HPCA, pages 156--167, 1997.

....of execution time [35, 7] As with a conventional hierarchy, it is possible in principle to address the L1 cache virtually, in which case the TLB would only be needed on a miss to the SRAM main memory. Similar problems to those found in virtually addressed caches in a conventional hierarchy [21, 41, 35, 22] would apply. This possibility is not explored in this paper. 2.4 DRAM Paging Device The DRAM paging device is a conventional DRAM, which can be implemented using the same range of design choices as a conventional DRAMmainmemory. Details of the DRAM are not changed from previous work [33] to ....

.... features like memory management [3] In the 1980s, there was some work on software based management of caches, with emphasis on reduction of misses in a sharedmemory system [9, 8] More recently, work on managing the interface between cache and DRAM in software has focused on address translation [35, 22]. Other software based approaches have not gone as far as treating the lowest level of cache as a fully software managed paged memory (in effect, an SRAM main memory) 4 Simulated Systems 4.1 Introduction This section describes parameters of the simulated systems. The alternatives measured are ....

B. Jacob and T. Mudge. Software-managed address translation. In Proc. Third Int. Symp. on High-Performance Computer Architecture, pages 156--167, San Antonio, Texas, February 1997.

....of TLB miss traps will increase in future microprocessors. Proposed solutions to this growing TLB performance bottleneck range from changing the TLB structure to retain more of the working set (e.g. multi level TLB hierarchies [1, 16] to implementing better management policies (in software [21] or hardware [20] to masking TLB miss latency by prefetching entries (again, in software [4] or hardware [41] All of these approaches can be improved by exploiting superpages. Most commercial TLBs support superpages, and have for several years [30, 43] but more research is needed into how ....

B. Jacob and T. Mudge. Software-managed address translation. In Proceedings of the Third Annual Symposium on High Performance Computer Architecture, pages 156--167, Feb. 1997. 33

....of TLB miss traps will increase in future microprocessors. Proposed solutions to this growing TLB performance bottleneck range from changing the TLB structure to retain more of the working set (e.g. multi level TLB hierarchies [1, 8] to implementing better management policies (in software [10] or hardware [9] to masking TLB miss latency by prefetching entries (again, in software [2] or hardware [25] All of these approaches can be improved by exploiting superpages. Most commercial TLBs support superpages, and have for several years [16, 28] but more research is needed into how ....

B. Jacob and T. Mudge. Software-managed address translation. In Proc. of the Third HPCA, pp. 156--167, Feb. 1997.

....and changes [NUS 93, CLK97] micro TLBs [CBJ92] variable page sizes [CBJ92, TKHP92, KTNW93, ROKB95] and subblocking [Tal95] have been examined and incremental improvements made in effective TLB coverage. TLBs have been removed altogether in some experimental systems [WEG 86, CSD86, JM97] which perform address translation in the cache; however, the tech CHAPTER 4. GUARDED PAGE TABLE EVALUATION 38 niques have yet to appeared in a commercial microprocessor. There is little to suggest that minimising the TLB refill penalty will be of lower importance in the future than it is now. ....

Bruce Jacob and Trevor Mudge. Software-managed address translation. In Proc. 3rd High-Performance Computer Architecture Conference. IEEE, 1997.

....of TLB miss traps will increase in future microprocessors. 3 Proposed solutions to this growing TLB performance bottleneck range from changing the TLB structure to retain more of the working set (e.g. multi level TLB hierarchies [1, 9] to implementing better management policies (in software [12] or hardware [11] to masking TLB miss latency by prefetching entries (in software [2] or hardware [23] All of these approaches can be improved by exploiting superpages. Most TLBs now support superpages, and have for several years [16, 27] but more research is needed into how best to make ....

B. Jacob and T. Mudge. Software-managed address translation. In Proc. of the Third HPCA, pp. 156-167, Feb. 1997.

....cache system, and a RAMpage system. Note that the major components are the same. Both systems use the same amount of SRAM, and both have a TLB to cache recent page translations; the difference is in the way they are managed. The RAMpage hierarchy extends earlier work on software managed caches [8, 7, 6, 19] by going all the way to implementing what was previously the lowest level of cache as a paged memory. There are two major differences between the RAMpage strategy and earlier work on software menaged caches: ffl hits can be handled immediately if the TLB hits, without the overhead of cache tag ....

.... 4 way set associative caches [6] Other more recent work on software controlled caches was designed to do efficient address translation on a miss with a virtually addressed cache, and is therefore not closely related to the problem RAMpage is addressing (caches in this work were direct mapped) [19]. 2.3 RAMpage Versus Other Solutions Other solutions to the CPU DRAM speed gap generally at best hide the underlying trend, they do not provide a scalable way of working around it. A modest reduction in the number of misses to DRAM (as in approaches to improve direct mapped caches) simply ....

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B Jacob and T Mudge. `Software-managed address translation'. In Proceedings of the Third International Symposium on High-Performance Computer Architecture, San Antonio, Texas, (February 1997).

....page table organizations and page size similar to our solution. However, the key difference between Hot Pages and AVM is that Hot Pages implements specialization of resource management based on static compile time information. The Softwm approach for software address translation proposed in [9] implements address translation in software similar to our system but without leveraging compile time information. Although it obtains low overhead for virtualization, the approach taken is mainly applicable in the case of virtually tagged and addressed caches where address translation is not on ....

B. Jacob and T. Mudge. Software-Managed Address Translation. In Proceedings of the 24nd Annual International Symposium on Computer Architecture, 1997.

....which is clearly a harder sell. In the 1980s, there was some work on software managed caches, with emphasis on reduction of misses in a shared memory system [CSB86, CGBG88] More recently, work on managing the interface between cache and DRAM in software has focussed on address translation [JM97] In neither case has the major focus been on achieving a higher degree of associativity than is common in caches; the space created by high miss costs has been exploited for other reasons. Also, the possibility of increasing block size to allow room in a miss for doing other useful work has not ....

B Jacob and T Mudge. Software-managed address translation. In Proceedings of the Third International Symposium on High-Performance Computer Architecture, San Antonio, Texas, February 1997.

....page table organizations and page size similar to our solution. However, the key difference between Hot Pages and AVM is that Hot Pages implements specialization of resource management based on static compile time information. The Softwm approach for software address translation proposed in [7] implements address translation in software similar to our system but without leveraging compile time information. Although it obtains low overhead for virtualization, the approach taken is mainly applicable in the case of virtually tagged and addressed caches where address translation is not on ....

B. Jacob and T. Mudge. Software-Managed Address Translation. In Proceedings of the 24nd Annual International Symposium on Computer Architecture, 1997.

.... In a multiprocessor, the effective amount of TLB does not increase as fast as the number of processors because entries are replicated; moreover, TLB consistency must be maintained[27] Virtual address caches have been proposed to relieve the latency and bandwidth requirements of TLBs[5] 6] 11][15][32] When the cache is virtually indexed and tagged, most memory accesses are completed without TLB involvement; in fact, address translation can be done in different locations in the memory hierarchy[29] and can be implemented in various ways, such as in cache translation[32] or even by ....

.... When the cache is virtually indexed and tagged, most memory accesses are completed without TLB involvement; in fact, address translation can be done in different locations in the memory hierarchy[29] and can be implemented in various ways, such as in cache translation[32] or even by software[15]. In this paper we explore design options to reduce address translation overhead and make it more scalable, especially in multiprocessor systems. The basic idea is to move the address translation closer to memory, where the TLBs are shared, do not have coherence problems, and scale well with ....

[Article contains additional citation context not shown here]

Bruce Jacob and Trevor Mudge. "Software-Managed Address Translation," In Proceedings of the 3rd International Symposium on High Performance Computer Architecture(HPCA), Feb. 1997.

....is clearly a harder sell. In the 1980s, there was some work on software based management of caches, with emphasis on reduction of misses in a sharedmemory system [CSB86, CGBG88] More recently, work on managing the interface between cache and DRAM in software has focused on address translation [JM97] In neither case has the major focus been on achieving a higher degree of associativity than is common in caches; the space created by high miss costs has been exploited for other reasons. Also, the possibility of increasing block size to allow room in a miss for doing other useful work has not ....

B. Jacob and T. Mudge. Software-managed address translation. In Proc. Third Int. Symp. on HighPerformance Computer Architecture, San Antonio, Texas, February 1997.

....instruction for writing into instruction memory [Gwennap99] These mechanisms have uses beyond just code compression. Jacob et al. propose using such features to replace hardware managed address translation performed by the translation lookaside buffer with software managed address translation [Jacob97]. Jacob further suggests using software managed caches to provide fast, deterministic memories in embedded systems [Jacob99] The following sections describe new instructions added to the SimpleScalar simulator to support software decompression. First, the swic instruction for modifying the cache ....

B. Jacob and T. Mudge, "Software-Managed Address Translation", Proceedings of the Third International Symposium on High Performance Computer Architecture, pp. 156-167, 1997.

....then the wildly incompatible designs They only serve to make the porting of applications and operating systems more difficult. With increasing cache sizes (especially the multi megabyte L2 caches of today s workstations) a simple solution may be to eliminate memory management hardware completely [7]. If systems used large virtually indexed, virtually tagged cache hierarchies, hardware address translation would be unnecessary; virtual caches require no address translation, and if the caches are large enough one will rarely need to go to main memory. Address translation would be performed only ....

B. L. Jacob and T. N. Mudge. "Software-managed address translation." In Proc. Third International Symposium on High Performance Computer Architecture (HPCA-3), San Antonio TX, February 1997.

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B.L. Jacob and T.N. Mudge, "Software-Managed Address Translation," Proc. HPCA-3, IEEE CS Press, Feb. 1997, pp. 156-167; http:// computer.org/conferen/hpca97/77640156.pdf.

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Bruce Jacob and Trevor Mudge. Software-managed address translation. In Proc. 3rd HPCA, pages 156--167, 1997.

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Bruce Jacob and Trevor Mudge. Software-managed address translation. In Proc. 3rd HPCA, pages 156--167, 1997.

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Jacob, B. and Mudge, T. (1997). Software-managed address translation. In Proc. Third Int. Symp. on HighPerformance Computer Architecture, pages 156--167, San Antonio, TX.

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B. Jacob and T. Mudge. Software-managed address translation. In Proc. Third Int. Symp. on HighPerformance Computer Architecture, pages 156--167, San Antonio, Texas, February 1997.

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B. Jacob and T. Mudge. Software-managed address translation. In Proceedings of the Third International Symposium on High Performance Computer Architecture, pages 156--167, Los Alamitos, CA, 1997. IEEE Computer Society Press.

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B. Jacob and T. Mudge. Software-managed address translation. In Proceedings of the Third IEEE Symposium on High Performance Computer Architecture, pages 156-167, San Antonio, TX USA, Feb. 1997.

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B. Jacob and T. Mudge. Software-managed address translation. In Proc. Third Int. Symp. on High-Performance Computer Architecture, pages 156--167, San Antonio, TX, February 1997.

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