W. Dally, S. Keckler, N. Carter, A. Chang, M. Fillo, and W. Lee. M-Machine Architecture v1.0. Technical Report MIT Concurrent VLSI Architecture Memo 58, Artificial Intelligence Laboratory, Massachusetts Institute of Technology, 1994. Home/Search Document Not in Database Summary Related Articles Check |
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Communication Performance of Wormhole Interconnection Networks - Petrini (1997) (Correct)
....be considered as an algorithm design optimization. In response to the incentives to reduce communication overhead in parallel computers several machines have been envisioned in which more of the network communication mechanisms are handled in hardware, e.g. the J machine [39] and the M machine [34] or in specialized network interfaces [43] 109] 55] Such decreases in the overhead of a communication increase the relative importance of network topology. Yet contention based latency is a complicated function of topology and the communication pattern, and while topological considerations may ....
W. Dally, S. Keckler, N. Carter, A. Chang, M. Fillo, and W. Lee. M-Machine Architecture v1.0. Technical Report MIT Concurrent VLSI Architecture Memo 58, Artificial Intelligence Laboratory, Massachusetts Institute of Technology, 1994.
Simultaneous Multithreading: Maximizing On-Chip Parallelism - Tullsen, Eggers, Levy (1995) (210 citations) (Correct)
....all issue slots can be filled in a cycle. Superscalar execution (as opposed to single issue execution) both introduces horizontal waste and increases the amount of vertical waste. ventional multiprocessor. As chip densities increase, single chip multiprocessors will become a viable design option [7]. The simultaneous multithreaded processor and the single chip multiprocessor are two close organizational alternatives for increasing on chip execution resources. We compare these two approaches and show that simultaneous multithreading is potentially superior to multiprocessing in its ability to ....
....threads during the same cycle. In fact, most of these architectures are single issue, rather than superscalar, although Tera has LIW (3 wide) instructions. In Section 4, we extended these results by showing how fine grain multithreading runs on a multiple issue processor. In the M Machine [7] each processor cluster schedules LIW instructions onto execution units on a cycle by cycle basis similar to the Tera scheme. There is no simultaneous issue of instructions from multiple threads to functional units in the same cycle on individual clusters. Franklin s Multiscalar architecture [13, ....
W.J. Dally, S.W. Keckler, N. Carter, A. Chang, M. Fillo, and W.S. Lee. M-Machine architecture v1.0. Technical Report -- MIT Concurrent VLSI Architecture Memo 58, Massachusetts Institute of Technology, March 1994.
A Comparison of Wormhole-Routed Interconnection Networks - Petrini, Vanneschi (1997) (Correct)
No context found.
W. Dally, S. Keckler, N. Carter, A. Chang, M. Fillo, and W. Lee. M-Machine Architecture v1.0. Technical Report MIT Concurrent VLSI Architecture Memo 58, Artificial Intelligence Laboratory, Massachusetts Institute of Technology, 1994.
Design and Performance of Multithreaded Architectures - Thekkath (1995) (Correct)
No context found.
W.J. Dally, S.W. Keckler, N. Carter, A. Chang, M. Fillo, and W.S. Lee. M-Machine architecture v1.0. Technical Report MIT Concurrent VLSI Architecture Memo 58, Massachusetts Institute of Technology, March 1994. 92
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