Giovanni De Micheli. Synchronous Logic Synthesis. IEEE Transactions on Computer Aided Design, 10(1), January 1991. Home/Search Document Not in Database Summary Related Articles Check |
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Retiming Sequential Circuits for Low Power - Monteiro, Devadas, Ghosh (1993) (30 citations) (Correct)
....is more desirable from a power standpoint. The circuits may also have differing performance. We utilize the above observations in a heuristic retiming strategy that targets power dissipation as its primary cost function. 4 Retiming for Low Power Retiming algorithms that minimize clock periods [5, 6] rely on the fact that delay varies linearly under retiming. Unfortunately that is not so with switching activity. The retiming of a single node can dramatically change the switching activity in a circuit and it is very difficult to predict what this change will be. Further, estimating the ....
Giovanni De Micheli. Synchronous Logic Synthesis. IEEE Transactions on Computer Aided Design, 10(1), January 1991.
Retiming Sequential Circuits for Low Power - Jose Monteiro Srinivas (1993) (30 citations) (Correct)
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Giovanni De Micheli. Synchronous Logic Synthesis. IEEE Transactions on Computer Aided Design, 10(1), January 1991.
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