C. Huizer, "Power Dissipation Analysis of CMOS VLSI Circuits by Means of Switch-Level Simulation," Proceedings of the European Solid-State Circuits Conference `90, pp. 61-64, 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the vast majority of work of other researchers who also considered only external capacitance charging and discharging in their power models. Existing techniques for power estimation at gate and circuit level can be divided in two main classes: dynamic and static [1] 25] Dynamic techniques [2], 3] explicitly simulate the circuit under a typical input stream. Consequently, their results depend on the simulated sequence, and the required number of simulated vectors is usually high. These techniques can provide sufficient accuracy at the expense of large running times. Switching ....

C. M. Huizer, "Power dissipation analysis of CMOS VLSI circuits by means of switch-level simulation," in Proc. IEEE European Solid-State Circuits Conf., 1990, pp. 61--64.

....applicable only for combinational circuits. For sequential circuits various approaches [56] 59] have been proposed which assume that the future of FSM is dependent only on its present state and independent of its past state. As opposed to simulation based techniques, statistical techniques [34, 35, 36] do not require any specialized models for the components. The idea is to simulate the circuit with randomly generated input vectors until power converges to the average power. The convergence is tested by statistical mean estimation techniques. 2.2 Architectural Level of Abstraction At the ....

C. M. Huizer, "Power Dissipation analysis of CMOS VLSI circuits by means of switch level simulation",IEEE European Solid State Ciruits Conference, Grenoble, France, pp. 61-64,1990.

....macro model equations for highlevel design components, which are found in the library by plugging the parameter values in the corresponding macro model equations. 4) Estimate the power dissipation for random logic or interface circuitry by simulating the gate level description of these components [25], 26] or by performing probabilistic power estimation [27] 31] The low level simulation can be significantly sped up by the application of statistical sampling techniques [32] 35] or automata based compaction techniques [36] 38] The macro model for the components may be parameterized in ....

C. M. Huizer, "Power dissipation analysis of CMOS VLSI circuits by means of switch-level simulation," in Proc. IEEE Eur. Solid State Circuits Conf., 1990, pp. 61--64.

....variable is a cumulative distribution function. Thus, the tasks of estimating the average and maximum power dissipation reduce to that of estimating the mean and upper bound of the random variable. A number of techniques have been proposed to estimate the average and maximum power consumption [1, 2, 3, 4, 5]. For estimating the maximum power consumption, existing techniques can be classified into two classes: statistical techniques and deterministic techniques. In statististical techniques [6] the maximum power consumption is estimated using order statistics derived from a simple randomsample. In ....

C. M. Huizer. Power dissipation analysis of CMOS VLSI circuits by means of switch-level simulation. In IEEEEuropean Solid State Circuits Conf., pages 61-- 64, 1990.

....from a speed or accuracy point of view. Switch level simulation [6,7] is a very fast simulation approach, but has the limitation that it only treats signals as logic zero and one and does not calculate accurate delays. Power estimation using standard switch level simulation was reported in [8] using a commercially available simulator. However, exact values of node potentials were not calculated, and short circuit power was not estimated. The importance of obtaining the exact values of node potentials for power estimation is a consequence of the fact that only part of the nodes in ....

C.M.Huizer. "Power Dissipation Analysis of CMOS VLSI Circuits by Means of Switch-Level Simulation", Proc. of 16th European Solid-State Circuit Conf., 1990, p.61.

....and how to decide when the measured power has converged close enough to the true average power. Normally, the inputs are randomly generated and statistical mean estimation techniques [38] are used to decide when to stop essentially a Monte Carlo method. 3.2.3.1. Total power This approach [29, 30] uses Monte Carlo simulation to estimate the total average power of the circuit. It consists of applying randomly generated input patterns at the primary inputs and monitoring the energy dissipated per clock cycle using a simulator, until the cumulative power measured has converged to the true ....

C. M. Huizer, "Power dissipation analysis of CMOS VLSI circuits by means of switch-level simulation," IEEE European Solid State Circuits Conference, pp. 61--64, 1990.

....the power. These vectors are generated from user specified probabilistic information about the circuit inputs. Using statistical estimation techniques, one can determine when to stop the simulation in order to obtain a certain specified error bound. Details of these techniques can be found in [29 32], and will be summarized below. All of the above probabilistic and statistical techniques are applicable only to combinational circuits. They require the user to specify information on the activity at the latch outputs. Power estimation in sequential circuits will be discussed in section 6. 4. ....

....Statistical techniques. Approach Handle Toggle Power Handle Temporal Correlation Input Specification Individual Gate Power Handle Spatial Correlation Speed McPower Yes Yes Simple No Only Internally Fast MED Yes Yes Simple Yes Only Internally Moderate 5.1. Total power (McPower) This approach [29 31] uses Mont e Carlo simulation to estimate the total average power of the circuit. It consists of applying randomly generated input patterns at the primary inputs and monitoring the energy dissipated per clock cycle using a simulator. If the successive input patterns are independently generated, a ....

C. M. Huizer, "Power dissipation analysis of CMOS VLSI circuits by means of switchlevel simulation," IEEE European Solid State Circuits Conference, pp. 61--64, Grenoble, France, 1990.

....the power. These vectors are generated from user specified probabilistic information about the circuit inputs. Using statistical estimation techniques, one can determine when to stop the simulation in order to obtain a certain specified error bound. Details of these techniques can be found in [29 32], and will be summarized below. All of the above probabilistic and statistical techniques are applicable only to combinational circuits. They require the user to specify information on the activity at the latch outputs. The status of power estimation in sequential circuits will be discussed in ....

....Statistical techniques. Approach Handle Toggle Power Handle Temporal Correlation Input Specification Individual Gate Power Handle Spatial Correlation Speed McPower Yes Yes Simple No Only Internally Fast MED Yes Yes Simple Yes Only Internally Moderate 5.1. Total power (McPower) This approach [29 31] uses Mont e Carlo simulation to estimate the total average power of the circuit. It consists of applying randomly generated input patterns at the primary inputs and monitoring the energy dissipated per clock cycle using a simulator. If the successive input patterns are independently generated, a ....

C. M. Huizer, "Power dissipation analysis of CMOS VLSI circuits by means of switchlevel simulation," IEEE European Solid State Circuits Conference, pp. 61--64, Grenoble, France, 1990.

....sufficient accuracy is obtained in much less time than is required to compute the individual gate powers. The excellent speed performance and the simplicity of the implementation make this a very attractive approach for power estimation. An approach similar to this was independently proposed in [6], but the treatment there is not very rigorous and overlooks some important issues. Furthermore, no comparisons were performed with other approaches to show the superiority of the approach. In this paper, we present a rigorous treatment that provides the theoretical justification of this method. ....

C. M. Huizer, "Power dissipation analysis of CMOS VLSI circuits by means of switchlevel simulation," IEEE European Solid State Circuits Conference, pp. 61--64, Grenoble, France, 1990.

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C. Huizer, "Power Dissipation Analysis of CMOS VLSI Circuits by Means of Switch-Level Simulation," Proceedings of the European Solid-State Circuits Conference `90, pp. 61-64, 1990.

No context found.

C. M. Huizer, "Power Dissipation Analysis of CMOS VLSI Circuits by means of SwitchLevel Simulation," IEEE European Solid State Circuits Conference, pp. 61-64, 1990.

No context found.

C. M. Huizer. "Power dissipation analysis of CMOS VLSI circuits by means of switch-level simulation," IEEE European Solid State Circuits Conf., 1990, pages 61--64.

No context found.

C. M. Huizer, "Power Dissipation Analysis of CMOS VLSI Circuits by means of Switch-Level Simulation," IEEE European Solid State Circuits Conference, pp. 61-64, 1990.

No context found.

C. M. Huizer, `Power Dissipation Analysis of CMOS VLSI Circuits by means of Switch-level Simulation', in Proc. IEEE European Solid State Circuits Conf., pp. 61-64, 1990.

No context found.

C. M. Huizer. Power dissipation analysis of cmos vlsi circuits by means of switch-level simulation. In IEEE European Solid State Circuits Conf., pages 61--64, 1990.

No context found.

C. M. Huizer, "Power Dissipation Analysis of CMOS VLSI Circuits by means of Switch-Level Simulation," IEEE European Solid State Circuits Conf., pp. 61-64, 1990.

No context found.

C. M. Huizer, "Power Dissipation analysis of CMOS VLSI circuits by means of switch level simulation", IEEE European Solid State Ciruits Conference, Grenoble, France, pp. 61-64,1990.

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