D. Ku and G. D. Micheli. High-Level Synthesis of ASICs under Timing and Synchronization Constraints. Kluwer Academic Publishers, 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....component timing. This is possible since in most cases, component control is single threaded following a fixed control sequence which only depends on input patterns. Optimization is concerned with an optimal static schedule of operations. Behavioral synthesis closely follows this approach [7]. Embedded software adds process preemption to enable another class of scheduling strategies. Preemptive and time driven scheduling introduces timing dependencies between functionally independent processes. Heterogeneous platforms take the next step of target system complexity combining several ....

David C. Ku and Giovanni de Micheli. High-Level Synthesis of ASICs Under Timing and Synchronization Constraints. Kluwer Academic Publishers, Boston, Massachusetts, 1992.

.... point of view the most convenient in such a complex circuit, is to design an abstract model with all the characteristics and features of the real circuit, and then simply test if the outputs of the behavioral and the structural model are the same(when the inputs are the same, of course) McCl86] [KuMi92]. The reason whywe trust this method is mainly that this model is likely to be programmed in a high level programming language and as a result is more easily debugged, since we can use the useful features of the compiler. Thus, we can assume that the output of the behavioral model is the correct, ....

D. Ku, G. De Micheli: "High level synthesis of ASICs under timing and synchronization constraints", Kluwer Academic Publishers, 1992.

....C model is presented along with examples of bugs found in our design using equivalence checking. 2. RELATED WORK Several C C coding styles have been used in the past two decades in the industry [17,24] as well as in the research community to describe hardware both for modeling and synthesis [7,20]. In general, the C C language is both extended and restricted [15] It is extended to support hardware data types such as bit vector, 3 state logic, etc. and, sometimes, to support parallelism using communicating processes and reactivity. On the other hand the C C lan Permission to make ....

David Ku and Giovanni De Micheli, "High-Level Synthesis of ASICs under Timing and Synchronization Constraints", Kluwer Academic Publishers, Boston, MA 1992.

....and interaction of rephasing with other high level synthesis tasks. 2. Previous Work Relevant to the manipulation of timing relationships by rephasing is the handling of timing constraints that is done by the schedulers during high level synthesis. While there are several notable exceptions [Ku92, Fil93], most of high level synthesis work has been based on the synchronous dataflow model of computation. As pointed out earlier, most high level synthesis systems for DSP either assume that all input and delay node samples are available at the same time (all phases are zero) or indirectly assign ....

D. Ku, G. De Michelli: "High Level Synthesis of ASICs Under Timing and Synchronization Constraints ", Kluwer, Norwell, MA, 1992.

....[5] 6] 7] In addition to using traditional behavioral synthesis languages such as Verilog and VHDL, synthesis from software application languages such as C C or Java is also gaining popularity. Some of the systems that synthesize subsets of C C or C based languages include HardwareC [21], SystemC [22] and Esterel C [23] DeepC, a compiler for a variation of the RAW parallel architecture presented in [2] allows sequential C or Fortran programs to be compiled directly into custom silicon or reconfigurable architectures. Some other novel hardware synthesis systems compile Java ....

David Ku, and Giovanni De Micheli. High Level Synthesis of ASICs under Timing and Synchronization Constraints, Kluwer Academic Publishers, Boston, MA 1992.

....edges. The semantics underlying the syntax of the CDFG format is that of the SDF flow model. All developed EC techniques can be applied successfully to other computation models such as the discrete event, communicating FSMs, synchronous reactive, dataflow process network, and Petri net model [Ku92, Kif95, Edw97]. In addition, local watermarking is a generic approach and can be used for IPP of solutions or tools for many other combinatorial and continuous optimization problems. 3.2. Targeted Behavioral Synthesis Tasks Behavioral synthesis transforms a given behavioral specification into an RTL ....

D.C. Ku and G. De Micheli. High Level Synthesis of ASICs under Timing and Synchronization Constraints. Kluwer, Dordrecht, Netherlands, 1992.

....This technique, however, expands the graph by unfolding it. Furthermore, such an approach is limited to solving the problem without considering uncertain computation times for operations [5, 13] Some research considers the uncertainty inherit in the computation time of nodes. Ku and De Micheli [11, 12] proposed a relative scheduling method which handles tasks with unbounded delays. Nevertheless, their approach considers a DAG as an input and does not explore the parallelism across iterations. Furthermore, even if the statistics of the computation time of uncertain nodes is collected, their ....

D. Ku and G. De Micheli. High-Level synthesis of ASICS under Timing and Synchronization constraints. Kluwer Academic, 1992.

....in the synthesis process, e.g. Dey et al. 1992] However, there is a strong experimental evidence that they are most effective at the highest levels of abstractions, such as system and in particular behavioral synthesis. Transformations only received widespread attention in high level synthesis [Ku and Micheli 1992; Potkonjak and Rabaey 1992; Walker and Camposano 1991] Comprehensive reviews of use of transformations in parallelizing compilers, stateof the art general purpose computing environments, and VLSI DSP design are given in [Banerjee et al. 1993] Bacon et al. 1994] and [Parhi 1995] ....

Ku, D. and Micheli, G. D. 1992. High Level Synthesis of ASICs under Timing and Synchronization Constraints. Kluwer, Dordrecht, Netherlands.

....This technique, however, expands the graph by unfolding it. Furthermore, such an approach is limited to solving the problem without considering uncertain computation times for operations [5, 13] Some research considers the uncertainty inherit in the computation time of nodes. Ku and De Micheli [11, 12] proposed a relative scheduling method which handles tasks with unbounded delays. Nevertheless, their approach considers a DAG as an input and does not explore the parallelism across iterations. Furthermore, even if the statistics of the computation time of uncertain nodes is collected, their ....

D. Ku and G. De Micheli. High-Level synthesis of ASICS under Timing and Synchronization constraints. Kluwer Academic, 1992.

....researchers, most notably De Micheli, 1] suggested modeling behavioral specifications as hierarchical graphs. In such a representation one can conveniently model loop bodies as modules in the hierarchy as well. Ku and DeMicheli proposed relative scheduling algorithms for hierarchical graphs [12]. We use hierarchical modular specifications in this paper as described in detail in Section 2. Our register optimization algorithm is carrier based and is distinguished by its hierarchical optimization phase which attempts to achieve the same effect of global in line expansion without actually ....

....words, the description language does not influence the optimization algorithm. The description has a main( a function namely, gcd( and a procedure namely rem( 3 Scheduling Assumptions We assume that the register optimization phase follows the scheduling phase during high level synthesis [12, 13, 19]. The job of the scheduler is to assign a control step to each statement in a module, relative to the first statement in the module. Schedulers attempt to generate minimal length schedules subject to the given user specified constraints such as area, clock speed and available resources. In the ....

David C. Ku and G. De Micheli, "High Level Synthesis of ASICs Under Timing and Synchronization Conditions", Kluwer Academic Publishers, 1992.

....is proposed consisting of bottleneck identification and lifetime serialization. These two components are explained in more detail in the subsequent sections. Section 5 shows some experimental results. 2. Definitions and assumptions A DSP application can be expressed as a data flow graph (DFG) [7], which describes the primitive operations performed in the algorithm, and the dependencies between those operations. Definition 1 (Data Flow Graph) A data flow graph DFG is a triple (V, E d [ E s , w) where ffl V is the set of vertices (operations) ffl E d V Theta V is the set of data ....

D. Ku and G. D. Micheli, editors. High Level Synthesis of ASICs Under Timing and Synchronization Constraints. Kluwer Academic Publisher, 1992.

....and the global solution strategy is proposed in Section IV consisting of bottleneck identification and lifetime serialization. Section V shows some experimental results and Section VI some conclusions. II. Definitions and assumptions A DSP application can be expressed as a data flow graph (DFG) [8], which describes the primitive operations performed in the algorithm, and the dependencies between those operations. Definition 1 (Data Flow Graph) A data flow graph DFG is a triple (V, E d # E s , w) where: V is the set of vertices (operations) E d # V V is the set of data ....

D.C. Ku and G. De Micheli, Eds., High Level Synthesis of ASICs Under Timing and Synchronization Constraints, Kluwer Academic Publisher, 1992.

....in the form of a control data flow graph (CDFG) having loops with arbitrary nesting. Various approaches to scheduling in high level synthesis exist [1, 2, 7] Loop scheduling has been addressed in [4, 3] Ku and De Micheli have proposed hierarchical scheduling for real time constraints [5, 6]. In the presence of nested loops, the behavior specification is typically modelled as hierarchical CDFG structure where the CDFG in each level contains two types of nodes: simple nodes representing simple operations such as plus and minus and complex or loop nodes representing a loop structure ....

David Ku and G. De Micheli, "High Level Synthesis of ASICs under Timing and Synchronization Constraints", Kluwer, 1992.

....This technique, however, expands the graph by unfolding it. Furthermore, such an approach is limited to solving the problem without considering uncertain computation times for operations [5, 13] Some research considers the uncertainty inherit in the computation time of nodes. Ku and De Micheli [11, 12] proposed a relative scheduling method which handles tasks with unbounded delays. Nevertheless, their approach considers a DAG as an input and does not explore the parallelism across iterations. Furthermore, even if the statistics of the computation time of uncertain nodes is collected, their ....

D. Ku and G. De Micheli. High-Level synthesis of ASICS under Timing and Synchronization constraints. Kluwer Academic, 1992.

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D. C. Ku and G. De Micheli, High Level Synthesis of ASICs Under Timing and Synchronization Constraints, Kluwer Academic Publishers, Norwell, MA, 1992.

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D. Ku and G. De Micheli, High-Level Synthesis of ASICs Under Timing and Synchronization Constraints. Norwell, MA: Kluwer, 1992.

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D. Ku and G. De Micheli, High-Level Synthesis of ASICs Under Timing and Synchronization Constraints, Kluwer Academic Publishers, 1992.

....in the important property that the graph induced by the forward edges of the constraint graph is acyclic. In this paper, we focus on one level of the hierarchy because control synthesis and optimization can be performed by traversing the hierarchy in a bottom up fashion. The reader is referred to [8] for further details on the constraint graph model. We now describe the properties of the model that are important in the control formulation. The vertices V of the graph represent the operations, and the edges E capture the precedence and timing relationships among the operations. Each vertex v ....

D. C. Ku and G. DeMicheli, High Level Synthesis of ASICs Under Timing and Synchronization Constraints. Kluwer Academic Publishers, 1992.

....This task turns out to be particularly difficult because of dynamic memory allocation, function calls, recursions, goto s, type castings and pointers. Different subsets of C and C like HDLs have been defined and used for synthesis. We mention first those developed in the eighties. HARDWAREC [4] is a fully synthesizable language with a C like syntax and a cycle based semantic. It doesn t support pointers, recursion and dynamic memory allocation. CONES [12] from AT T Bell Laboratories is an automated synthesis system that takes behavioral models written in a C based language and ....

....struct int i; short ts[2] its; int a, b; its.i = a; b = its.i; Because of potential out of bound array accesses (e.g. its.t[ 1] the structure variable its is entirely represented by the location set its , 0, 2 . The code segment is then transformed into: short SPC its 0 2[4]; int SPC a 0 0, SPC b 0 0; its.i = a; SPC its 0 0[0] SPC a 0 0 16; SPC its 0 0[1] SPC a 0 0; b = its.i; SPC b 0 0 = SPC its 0 0[0] 16 SPC its 0 0[1] Note that, using a concatenation operator . these assignments can be written as: SPC my str 0 0[0] ....

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David Ku and Giovanni De Micheli, "High-Level Synthesis of ASICs under Timing and Synchronization Constraints," Kluwer Academic Publishers, Boston, MA 1992.

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D. Ku and G. D. Micheli. High-Level Synthesis of ASICs under Timing and Synchronization Constraints. Kluwer Academic Publishers, 1992.

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D. Ku and G. D. Micheli. High-level Synthesis of ASICs under Timing and Synchronization Constraints. Kluwer Academic Publishers, Borton/London/Dordrecht, 1992.

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D.C. Ku and G. De Micheli. High-level Synthesis of ASICs under Timing and Synchronization Constraints. Kluwer Academic Publishers, Boston, MA, 1992.

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D. Ku and G. De Micheli. High level synthesis of ASICs under timing and synchronization constraints. Kluwer Academic Publishers, 1992.

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Ku D. and De Micheli, G.: High-level Synthesis of ASICs under Timing and Synchronization Constraints. Kluwer Academic Publishers, 1992.

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D. Ku and G. De Micheli. High-Level synthesis of ASICS under Timing and Synchronization constraints. Kluwer Academic, 1992. 25 Paper #: 104958 Submitted to IEEE Transactions on Computers

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