R. Ho. On-Chip Wires: Scaling and Efficiency. PhD thesis, Stanford University, 2003. Home/Search Document Details and Download
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The Design and Implementation of a Low-Latency On-Chip Network - Robert Mullins Andrew (2006) (1 citation) (Correct)
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R. Ho. On-Chip Wires: Scaling and Efficiency. PhD thesis, Stanford University, 2003.
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