Z. Kohavi. Switching and Finite Automata Theory. McGraw Hill, 1978.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....2 ) produced by the faulty machine corresponding to f2 in response to Y when the machine starts in state S f 2 . Definition 2 (Indistinguishability (f1,f 2 ) 16] A fault pair (f1,f 2 ) is said to be indistinguishable if it is not distinguishable. Definition 3 (State Equivalence (S f 1 ,S f 2 ) [23, 24]) State S f 1 of a machine M f 1 corresponding to fault f1 and state S f 2 of a machine M f 2 corresponding to fault f2 are equivalent if and only if there is no input sequence Y such that the output sequences Z f 1 (Y,S f 1 ) produced by M f 1 in response to Y when the machine starts in state S f ....

Z. Kohavi, Switching and Finite Automata Theory, New York, NY: McGrawHill, 1978.

....(N 2) has been mentioned in section six. 2 PROTOCOL SPECIFICATIONS Network protocols should be described formally in a concise manner. A wide spectrum of specification approaches are available [1. 2] Certain network protocols can be described in terms of network states and state transitions [3,4]. However, the number of states for a complex protocol increases rapidly and makes this approach unfesasible. Petri net [5,6] developed by Carl Adam Petri, is another way of describing and analysing protocols. Backus Naur form (BNF) is a notation used for writing grammers that, inturn, specify ....

Z.Kohavi, Switching and Finite Automata Theory, McGraw-Hill, New York, 1970.

....[29] A user refined transition coverage model has been proposed [30] which selects only transitions which affect state variables which are identified by the user as being important for test. The problems associated with state machine testing are understood from classical switching theory [31] and are summarized in an thorough survey of on state machine testing [32] The most significant problem with the use of state machine fault models is the complexity resulting from the state space size of typical systems. Several efforts have been made to alleviate this problem by identifying a ....

....outputs. In this case, a distinguishing sequence must be applied to differentiate each state from all other states based on output values. The testing problems associated with state machines, including the identification of distinguishing, synchronizing, and homing sequences, are well understood [32, 31]. The abstraction method used to represent the state machine has been shown to greatly impact the complexity of the test generation process. Binary Decision Diagrams (BDDs) have been used to represent the state transition relation and efficiently perform implicit state enumeration by defining an ....

Z. Kohavi, Switching and Finite Automata Theory, McGraw Hill, 1978.

....revision (e.g. 8,12,16] Many systems for theory revision, such as EITHER [11] have been implemented. The problem of correcting errors is pervasive, and errorcorrecting algorithms appear in a variety of contexts. Among them are fault analysis of circuits in switching theory (see, e.g. Kohavi [7]) program debugging (e.g. 13] and modelbased diagnosis (see, e.g. 5, 9] See Sloan and Turan [14] for a somewhat longer discussion of these connections. Sloan and Turan [14] present a family of DNF formulae on n variables with O(n) terms for which any revision algorithm requires n) ....

Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, New York, NY, second edition, 1978.

....for various configurations of the timers. In addition to the original self loops of a specification model, additional self loops are typically created when generated test sequences use state verification techniques such as unique input output (UIO) sequences [58] distinguishing sequences [5] [42], or characterizing sequences [5] 42] A.2 Optimizing Tests under Timing Constraints Let E self and E vnsl be the sets of self loop and non self loop edges to be tested, respectively. Let d self (v i ) the number of self loops of vertex v i , be defined as the number of edges in E self ....

.... In addition to the original self loops of a specification model, additional self loops are typically created when generated test sequences use state verification techniques such as unique input output (UIO) sequences [58] distinguishing sequences [5] 42] or characterizing sequences [5] [42]. A.2 Optimizing Tests under Timing Constraints Let E self and E vnsl be the sets of self loop and non self loop edges to be tested, respectively. Let d self (v i ) the number of self loops of vertex v i , be defined as the number of edges in E self incident on v i . Let d min self (v i ) be ....

Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, New York, NY, 1978.

....= 1 ) f(a x 0 ) 1. The function f is unate in x if it is either monotone or anti monotone in x. A Boolean function is monotone if it is monotone in all its input variables. It is unate if it is unate in all its input variables. Unate functions have been studied extensively in switching theory [6, 7]. More recently, they have been exploited in the development of algorithms in computational learning theory [1, 3] The class of monotone Boolean functions has a simple characterization in terms of forbidden projections. The class consists of exactly those functions that do not have any ....

Z. Kohavi, Switching and Finite Automata Theory (McGraw-Hill, New York, 1978).

....function. The problem of confirming that an implementation properly places procedure arguments is equivalent to experimentally determining if the implementation behaves as described by the P FSA state table. This problem is known as the checking experiment problem from finite automata theory [8, 9]. There are numerous approaches to this problem, most of which are based on transition testing. Transition testing forces the implementation to undergo all the transitions that are specified in the specification FSA. An obvious first approach to generating test vectors using the P FSA ....

....the implementation of a communication protocol adheres to the protocol s specification. Often, the protocol specification is provided as a finite state machine. This has resulted in many methods of test selection including the Transition tour, Partial W method [11] Distinguishing Sequence Method [9], Machine Transition Paths Transition Pair Paths Acyclic Paths DEC VAX 3 12 3 M68020 (Sun) 24 324 96 SPARC (Sun) 224 7,434 10 M88100 (Motorola) 720 22,412 10 MIPS R3000 (DEC) 772 5,655 810 Table III. Sizes of test suites for various selection methods. and Unique Input Output method [12] ....

Z. Kohavi, Switching and Finite Automata Theory. McGraw-Hill, second ed., 1978.

....for various configurations of the timers. In addition to the original self loops of a specification model, additional self loops are typically created when generated test sequences use state verification techniques such as unique input output (UIO) sequences [63] distinguishing sequences [6, 46], or characterizing sequences [6, 46] 3.1.2 Optimizing Tests under Timing Constraints 46587:9 ; and4 = 5279 be the sets of self loop and non self loop edges to be tested, respectively. BC5A7A9D;FEHGJILK , the number of self loops of vertex , be defined as the number of edges in ....

....the timers. In addition to the original self loops of a specification model, additional self loops are typically created when generated test sequences use state verification techniques such as unique input output (UIO) sequences [63] distinguishing sequences [6, 46] or characterizing sequences [6, 46]. 3.1.2 Optimizing Tests under Timing Constraints 46587:9 ; and4 = 5279 be the sets of self loop and non self loop edges to be tested, respectively. BC5A7A9D;FEHGJILK , the number of self loops of vertex , be defined as the number of edges in 4N5A7:9 ; a) v i ....

Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, New York, NY, 1978.

....visits all the edges of M at least once and comes back to s i . D method: In Distinguishing Sequence method [6] there is a sequence of inputs I, called DS, When applied to all states of M, results in di erent outputs. One method of generating DS is to nd the minimal covering of (i, DS diagram) [7] (where i 2 I and the symbol denotes the concatenation operation on string) W method: Characterizing Sequence method [5] is used only when M does not have a DS. The idea here is to concatenate some more input transitions to form a partial DS, called CS, that distinguishes a state from a ....

....at the beginning of second sub sequence. Now, the solution to test sequence generation problem is to make a tour of the TSG Graph. The algorithm to generate protocol test sequence using the proposed method is given below: Algorithm TSG TSP var i,j,k : int; 1. Generate the MUIOS as given in [7]. 2. Construct TSG graph TSG(N,B) 3. Select an INODE in TSG(N,B) 4. Construct TSG(n,n) and TSP(n,n) matrices, n is number of nodes. 6 5. Call TSP HNN with TSP(n,n) as input, obtain the tour vector R. 6.Calculate the test sequence, TS, using the tour vector, R as follows: k=0; TS = ....

Z.Kohavi,"Switching and Finite automata theory", Mc Graw Hill, New York, 1978.

....one of the successor tokens is an Any bit token and it overlaps with one of the other successor tokens, the any bit token must be split since any bit tokens match all bit patterns. Algorithms for subtracting a bit pattern from another can be found in many books on logic synthesis, see for instance [73, 74]. After the grammar has been reduced, only unique transitions remain. The Grammar DAG has been converted into a Deterministic Finite Automaton (DFA) Some situations during the token merging requires special attention. If a token has multiple predecessors, one copy of the token for every ....

....In step 4 a) state minimization is performed on the grammar DAG. Since the grammar DAG is a transition graph, it is easily converted into a THG. Although the state minimization algorithm [paper VII] has worse worst time complexity than ordinary state minimization algorithms performed on the STG [73, 74], the THG algorithm perform better for protocols that have long series of transitions and are very wide, i.e. they do not have so many alternative branches. Many framebased protocols exhibit these properties. In THG minimization, all out going edges from a transition node are viewed as a ....

Z. Kohavi, "Switching and Finite Automata Theory", McGraw-Hill, Inc., 1978.

....Scale Integration (VLSI) 1. INTRODUCTION In any VLSI design. there are always combinational switching functions that must be realized in silicon. XNe are proposing m mtomatic method for producing any combinational switching function (a function whose outputs depend only on the circuit inputs [1] with combining operators AND and OR) for CMOS layout. The error free layout we generate is optimal in most cases, where optimal is defined by sharing diffusion (eliminating intertransistor gaps) as much as possible. The algorithm we use is based on an algebra that describes the combination of ....

....in [ symbols. The name of the algebraic symbol and the representative graphs in that symbol are also shown at each node. The name is to the left of the graphs and is followed by a : On the lower right side of each representative graph is its value of 7 as computed for this expression. a] [1] [c] a] e] Figure 16. Assigning of algebraic symbols to nodes in the tree. There are some additional details of the first phase that need to be pointed out. The lineage of each representative graph in each algebraic symbol is saved. This information is needed during the layout phase so that ....

Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, (1978).

....# # # # # #### #### # # ## #######. To make the notation more compact we will use boldface lower case letters to denote vector boolean functions (VBFs) Over the last 15 20 years there have been many attempts to formalize the notions of equivalence and containment between two sequential machines [11, 20, 19, 8, 15]. In this paper we follow the notion of equivalence as defined below: Definition 1: Equivalence) Two sequential circuits # # and # # are called equivalent denoted by # # , # # iff for every state of ## there is at least one equivalent state of # # and for every state of # # there is at ....

Z. Kohavi. "Switching and Finite Automata Theory". McGraw-Hill Book Company, 1978.

....di questi algoritmi alla verifica, ed alla diagnosi, evidenziandone l applicabilita mediante i risultati sperimentali sui circuiti ISCAS 89 [BBKo89] comunemente usati come benchmark per il collaudo. 2 Le Macchine a Stati Finiti Una Macchina a Stati Finiti M e definita dalla 6 ennupla [Koha70]: M = I, O, S, #, #, s #IngressiP rimari #UsciteP rimarie I S # S I S # O. 5 # e la funzione di transizione degli stati, # e la funzione di uscita ed s e lo stato iniziale. 2.1 Classificazioni Tra le possibili classificazioni di FSM, la seguente distingue tra: ....

....dalle stesse specifiche, oppure una rappresenta la macchina priva di guasti e l altra una macchina con un guasto, come nel caso dell ATPG, oppure entrambe le macchine sono guaste, come nel caso della diagnosi. Il riferimento teorico per la dimostrazione della equivalenza e la Macchina Prodotto [Koha70]. Date due FSM M i e M j completamente specificate (M i = I, # i , # i , s i ) M j = I, # j , # j , s j ) la macchina prodotto M ij si definisce come: M ij = M i M j = I, B, S S, # ij , # ij , s #P rimaryInputs #P rimaryOutputs # ij (s ij , x) # i (s i ....

Z. Kohavi: "Switching and finite automata theory," Computer Science Series, Mc Graw Hill, New York, NY (USA), 1970

.... 3. The two choices for handling PB constraints in a SAT solver are 1) to convert them, in a pre processing step, to equivalent CNF constraints, and 2) to process them directly within the SAT solver. 3. 1 PB to CNF Conversion The PB constraint in (1) corresponds to a threshold Boolean function [12]. Such functions are unate (monotone) in each of their variables and have unique minimal CNF representations. Minimality here refers to the smallest CNF formula, among all functionally equivalent CNF formulas, namely the formula that has the fewest number of clauses provided there is no other such ....

Z. Kohavi, "Switching and Finite Automata Theory," Second ed. McGraw-Hill, 1978.

....for various configurations of the timers. In addition to the original self loops of a specification model, additional self loops are typically created when generated test sequences use state verification techniques such as unique input output (UIO) sequences [63] distinguishing sequences [6,47], or characterizing sequences [6,47] 2.2.2 Optimizing Tests under Timing Constraints Let # #### and # #### be the sets of self loop and non self loop edges to be tested, respectively. Let # #### ## # #, the number of self loops of vertex # # , be defined as the number of edges in # #### ....

....the timers. In addition to the original self loops of a specification model, additional self loops are typically created when generated test sequences use state verification techniques such as unique input output (UIO) sequences [63] distinguishing sequences [6,47] or characterizing sequences [6,47]. 2.2.2 Optimizing Tests under Timing Constraints Let # #### and # #### be the sets of self loop and non self loop edges to be tested, respectively. Let # #### ## # #, the number of self loops of vertex # # , be defined as the number of edges in # #### incident on # # .Let# ### #### ## # # be ....

Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, New York, NY, 1978.

....that an IUT can remain only for a limited amount of time in a given state during testing. UIO sequences [19] are used for state verification throughout the paper. However, the results presented also are applicable to test generation that uses the distinguishing or characterizing sequences [3, 12]. Two different test suites are considered. The first suite combines the testing of valid and inopportune transitions [11] An inopportune transition occurs when an IUT receives an input not expected in its current state. In general, an inopportune transition is modeled as a self loop, the ....

....optimization technique for generating realizable tests must consider the additional restriction that there is a limit on the number of self loop transitions traversed consecutively. OFF BOTHTIMERS ON TOP UPDATE TIMER ON TOP UPDATE REQ TIMER INACTIVE 25,26,30,32,35] ON 30,32,34,35] T[ 7,8,12,13,15,20, 25,30,32,35] T[ 7,8,10,12,13,14, 15,17,19,20,28,29, 30,32,34,35] T[ 2 6,7,8,25,26,32,35] T[ 9,11,16,18,22,27,33] T[ 9,11,16,18,22,27,29,33] T[23] T[23] T[21] T[24] T[31] T[29] T[31] T[31] T[31] T[1] T[21,29] T[24] Figure 1: Extended FSM for Topology Update module of MIL STD 188 220A. In ....

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Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, New York, NY, 1978.

....for various configurations of the timers. In addition to the original self loops of a specification model, additional self loops are typically created when generated test sequences use state verification techniques such as unique input output (UIO) sequences [51] distinguishing sequences [6, 37], or characterizing sequences [6, 37] 6.1.2 Optimizing Tests under Timing Constraints fhgjilknm fporqsgtk be the sets of self loop and non self loop edges to be tested, respectively. Let uvgjilknmxwzy t , the number of self loops of vertex , be defined as the number of edges in ....

....the timers. In addition to the original self loops of a specification model, additional self loops are typically created when generated test sequences use state verification techniques such as unique input output (UIO) sequences [51] distinguishing sequences [6, 37] or characterizing sequences [6, 37]. 6.1.2 Optimizing Tests under Timing Constraints fhgjilknm fporqsgtk be the sets of self loop and non self loop edges to be tested, respectively. Let uvgjilknmxwzy t , the number of self loops of vertex , be defined as the number of edges in fhglilk m incident on . Let uv nq ....

Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, New York, NY, 1978.

....(DAAL01 96 2 0002) Dr. Uyar, a Research Professor with Department of Electrical Engineering, the City College of the City University of New York, is presently Visiting Associate Professor at University of Delaware. test generation that uses the distinguishing or characterizing sequences [4, 11]. Earlier results of this study, limited to verification sequences that are self loops, are presented in [24] This paper generalizes these earlier results to both self loop and nonself loop verification sequences. Section 2 presents the practical motivation behind the optimization problem ....

....the data link protocol for the ISDN s D channel. In addition to the original self loops of a specification model, additional self loops are typically created when generated test sequences use state verification techniques such as unique input output (UIO) sequences [17] distinguishing sequences [4, 11], or characterizing sequences [4, 11] Example 2: Timing constraints in MIL STD 188 220B The University of Delaware s Protocol Engineering Laboratory is developing test scripts to be used by the U.S. Army CECOM in their MIL STD 188 220B Conformance Tester. Tests are being generated for both the ....

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Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, New York, NY, 1978.

....they can be input, for instance, to SRN networks. Each input representing a sequence of category preferences is associated with a sequence of corresponding output preferences. This simple description of sequence analysis is similar to the function of synchronous sequen tial machines [Booth, 1967, Kohavi, 1970, Shields, 1987] although preferences and learning are not yet considered in such machines. Therefore, we shall focus on extensions of synchronous sequential machines for representing sequential knowledge, especially synchronous Moore machines. We start with the basic definition of a synchronous ....

Kohavi, Z. (1970). Switching and Finite Automata Theory. McGrawHill, New York.

....whether a given stochastic activity network is wellspecified must check that the probability distribution over each next stable markings does not depend on the set of activity choices that is made. This condition can be checked using techniques developed to find the set of all maximal compatibles [20]. The following algorithm checks this for a particular stable marking and timed activity. Algorithm 1 (Determines whether the next stable marking probability distribution is invariant over possible sets of activity choices for a stable marking and activity a that can complete in , and if it is, ....

Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, New York, 1978.

....= s i ( x; q) i = 1; 2; n. To make the notation more compact we will use boldface lower case letters to denote vector boolean functions (VBFs) Over the last 15 20 years there have been many attempts to formalize the notions of equivalence and containment between two sequential machines [12, 19, 18, 9, 15]. In this paper we follow the notion of equivalence as defined below: Definition 1: Equivalence) Two sequential circuits C a and C b are called equivalent denoted by C a , C b iff for every state of C a there is at least one equivalent state of C b and for every state of C b there is at ....

Z. Kohavi. "Switching and Finite Automata Theory". McGraw-Hill Book Company, 1978.

....s 0 =o s 00 . We write M( for s M ( If for all , s( s 0 ( we write s s 0 . If s M s M 0 we write M M 0 . If not s s 0 (M M 0 ) we write s 6 s 0 (M 6 M 0 ) In case s 6 s 0 it is well known that s( 6 s 0 ( for some with j j jSj, see e.g. [7]. b 1 d e c 1,2 a b 1,3 a 0,2 b 1,3 a 0,2 b 1 c 1,2 s 0 s 1 s 2 s 3 s 4 s 5 Fig. 2. A nite state machine with initial state s 0 . 3 Let M [ denote M with all transitions s =o s 0 replaced by s =o 0 s 0 , where o 0 = o n f g. Intuitively, M [ means that is abstracted ....

Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, 1978.

....low complexity, namely, a sequence in the logspace uniform version of the complexity class AC 0 . Our main theorem relates nite state dimension to compressibility by information lossless nitestate compressors, which were introduced by Hu man [9] and have been extensively investigated. e.g. see [11] or [12] Speci cally, given such a compressor C and a sequence S 2 C, let C (S) denote the limit in mum of all compression ratios achieved by C on pre xes of S, and let FS (S) denote the in mum of all such C (S) Our main theorem says that dim FS (S) is precisely FS (S) Thus, with respect ....

....7 Dimension and Compression In this section we characterize the nite state dimensions of individual sequences in terms of nitestate compressibility. We rst recall the de nition of an information lossless nite state compressor. This idea is due to Hu man [9] Further exposition may be found in [11] or [12] De nition. A nite state compressor (FSC) is a 4 tuple C = Q; q 0 ) where Q is a nonempty, nite set of states, Q f0; 1g Q is the transition function, Q f0; 1g f0; 1g is the output function, and q 0 2 Q is the initial state. For q 2 Q and w 2 f0; 1g ....

Z. Kohavi. Switching and Finite Automata Theory (Second Edition). McGraw-Hill, 1978.

....If for all , s( s 0 ( we write s s 0 . If s M s M 0 we write M M 0 . If not s s 0 (M M 0 ) we write s 6 s 0 (M 6 M 0 ) It is obvious that is an equivalence relation. In case s 6 s 0 it is well known that s( 6 s 0 ( for some with j j jSj, see e.g. [8]. 2 Empty outputs and transitions to the same state with empty output are left out. s0 is the initial state. Singleton sets are represented by their contents. Another syntactical convention is that several transitions may Test Generation from Fault Models 3 A redirection is a function : E ....

Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, 1978.

....of the algorithm. The area of the implementations of benchmark machines obtained with the new synthesis method and with well known FSM tools are compared. 2 PRELIMINARIES 2. 1 Background For the sake of completeness some basic concepts in FSM synthesis will be briefly reviewed in this Section [12, 13]. An FSM can be formally defined as a quintuple M = I, S, O, where I is a finite set of inputs, S is a finite, non empty set, of states, O is a finite set of outputs, IS S is the next state function, and :IS O( S O) is the output function for a Mealy (Moore) machine. Either of ....

....the states which are merged into one state must be compatible and closure constraints must be satisfied [12] 14] These conditions are used as constraints in our encoding process. This is, the state reduction is achieved during the assignment process. Assigning an incompletely specified code [13] (group of codes) to a single state is equivalent to the transformation of the FSM symbolic description consisting in the substitution of a single state by a group of states (state splitting) and the assignment of this new description. There are two reasons to allow incompletely specified codes: ....

Z. Kohavi: "Switching and Finite Automata Theory". McGraw-Hill Book Company, New York, second edition, 1978.

....finite state systems, this theory is covered in numerous textbooks and in any basic undergraduate curriculum in computer science. Since its introduction in the 1950 s, the theory had numerous applications in practically all branches of computer science, from the construction of electrical circuits [Koh70], to the design of lexical analyzers [JPAR68] and to the automated verification of hardware and software designs [VW86] From its very inception, one fundamental theme in automata theory is the quest for understanding the relative power of the various constructs of the theory. Perhaps the most ....

Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, New York, 1970.

....(for the parity see [8] for Gray codes elementary considerations suce) It might be relevant to examine the relation between autosymmetric functions, and functions which are simply symmetric. That is, functions which are invariant under any permutation of their variables (see for example [7]) The total number of symmetric functions is N S = 2 n 1 , hence N S NA , but they are not a subset of the autosymmetric ones. In fact a symmetric function may be autosymmetric (e.g. the parity function) but there are symmetric functions that are not autosymmetric (e.g. any symmetric ....

Z. Kohavi. Switching and Finite Automata Theory. McGraw Hill, 1970.

....finite state systems, this theory is covered in numerous textbooks and in any basic undergraduate curriculum in computer science. Since its introduction in the 1950 s, the theory had numerous applications in practically all branches of computer science, from the construction of electrical circuits [11], to the design of lexical analyzers [10] and to the automated verification of hardware and software designs [30] Corresponding Author. Email addresses: nirp wisdom.weizmann.ac.il, vardi cs.rice.edu (Moshe Y. Vardi) URLs: http: www.wisdom.weizmann.ac.il nirp, ....

Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, New York, 1970.

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KOHAVI, Z. 1978. Switching and Finite Automata Theory. McGraw-Hill, Inc., New York, NY. KOLSON,D.J.,NICOLAU, A., AND DUTT, N. 1994. Minimization of memory traffic in high-level synthesis. In Proceedings of the 31st Annual Conference on Design Automation (DAC '94, San Diego, CA, June 6 --10), M. Lorenzetti, Chair. ACM Press, New York, NY, 149--154.

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Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, 1979.

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Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hill, 2nd edition, 1978.

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