Sanjiv Narayan and Daniel D. Gajski. Interfacing incompatible protocols using interface process generation. In DAC '95, 1995.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....use timing diagram specifications of protocols to construct event graphs and then generate a logic circuit which behaves as a transducer. Their technique requires that data buses have the same names and that the designer provide the information for correct merging of event graphs. Gajski et al.[14] decompose a protocol specification into a combinations five basic operations, and organise the protocol behaviour as ordered sets of guarded executions. Sets transferring the same amount of data are matched an interface is constructed. Data width, control and clock signal mismatches are handled ....

S. Narayan and D. D. Gajski. Interfacing incompatible protocols using interface process generation. Proceedings of the 32nd Design Automation Conference, June 1995.

....in [33] which was heuristically generated. Interface process generation also referred to as interface synthesis is the task of auto matically generating an interface process between incompatible protocols. There have been several attempts for the automatic generation of interface processes [7, 21, 12, 34, 3, 9] the starting point being the pioneering work by Borriello for automatic transducer synthesis [9] In this work, timing diagrams of the two custom hardware was presented as input and the system produced the logic specification of the required glue logic automatically. However this approach did not ....

....two custom hardware was presented as input and the system produced the logic specification of the required glue logic automatically. However this approach did not handle data width mismatches between the two incompatible hardware. This limitation was overcome in later work by Narayan and Gajski [34]. In this work the be haviours of the two incompatible blocks were represented in a hardware description language [49, 20] and then the algorithm verified if the two protocols were duals of each other. If they were not exact duals of each other then necessary extra control signals on either side ....

[Article contains additional citation context not shown here]

S. Narayan and D. d. Gajski. Interfacing incompatible protocols using interface process generation. In $2nd Design automation conference, pages 468-473, 1995.

....asyn chronous concurrent system interface modules. They take a high level description of the communication and insert the lower level details from a library into their internal Petri Net representation. Their approach is based on a Petri net al..gebra, described in [106] Narayan and Gajski [38], presents a method for interfacing incompatible protocols. They reduce the protocol specification to five atomic operations. These atomic operations are used to capture the protocol description. They take two incompatible protocols, analyse the protocol sequences and partition the protocols into ....

S. Narayan, D.D. Gajski, "Interfacing Incompatible protocols using interface process generation", In Proc. of DAC'95, pp. 468-473, 1995.

....in the form of parameters such as arbitration priorities, block transfer sizes, etc. Choosing appropriate values for these parameters can significantly impact the latency and transfer bandwidth associated with inter component communication. Finally, there is a body of work on interface synthesis [16, 17, 18, 19, 20, 21, 22, 23], which deals with automatically generating efficient hardware implementations for component to bus or component to component interfaces. These techniques address issues in the implementation of specified protocols, and not in the customization of the protocols themselves. In summary, we believe ....

S. Narayanan and D. D. Gajski, "Interfacing incompatible protocols using interface process generation, " in Proc. Design Automation Conf., pp. 468--473, June 1995.

....task. Alternatively, a set of different interface implementations may be provided with the source code from which one is selected by means of a HDL preprocessor. The disadvantage of this method clearly is that the module interface can only be adapted to a limited number of communication schemes. [7, 10, 6, 2, 1] describe algorithms for automatic generation of protocol conversion modules in form of FSM s that translate between incompatible protocols. The use of a protocol conversion module has the advantage that a modification of the module implementation is not necessary. However, additional hardware is ....

S. Narayan and D. Gajski. Interfacing incompatible protocols using interface process generation. In Proceedings of 32nd Design Automation Conference, 1995.

....task. Alternatively, a set of different interface implementations may be provided with the source code from which one is selected by means of a HDL preprocessor. The disadvantage of this method clearly is that the module interface can only be adapted to a limited number of communication schemes. [3, 4, 5, 6, 7] describe algorithms for automatic generation of protocol conversion modules in form of FSM s that translate between incompatible protocols. The use of a protocol conversion module has the advantage that a modification of the module implementation is not necessary. However, additional hardware is ....

S. Narayan and D. Gajski. Interfacing incompatible protocols using interface process generation. In Proceedings of 32nd Design Automation Conference, 1995.

....etc. usedbythechannels buses in the selected topology. The VSI Alliance on chip bus working group [14] has recognized that a multitude of bus protocols will be needed in order to serve the wide range of SOC communication requirements. Finally, there is a body of work on interface synthesis [15, 16, 17, 18, 19, 20, 21, 22], which deals with automatically generating efficient hardware implementations for component to bus or component to component interfaces. These techniques address issues in the implementation of specified protocols, and not in the customization of the protocols themselves. In summary, we believe ....

S. Narayanan and D. D. Gajski, "Interfacing incompatible protocols using interface process generation," in Proc. Design Automation Conf., pp. 468--473, June 1995.

....or generated. When the architecture is defined before, the protocol converter can be instantiated automatically from interface library since it is already generated before according to the architecture. For newly defined architectures, protocol converter should be generated using the algorithm in [13] and stored in the library for future instantiations. The signal register is generated in two phases register template selection and signal register allocation. In the register template selection phase, an appropriate template for signal register is selected from a template library according to ....

S. Narayan and D. Gajski. Interfacing incompatible protocols using interface process generation. Proc. 32nd Des. Auto. Conf., June 1995.

....hardware components and software components. The protocol converter connects the hardware core to the system bus of the target architecture by interfacing between the system bus and the signal registers. 1. Hardware Interface Generation The protocol converter is generated using the algorithm in [23]. Signal registers are generated in two phases register template selection and signal register allocation. In the register template selection phase, an appropriate template is automatically selected from a template library. Each template differs in the connection of multiplexers, decoders, ....

S. Narayan and D. Gajski, " Interfacing incompatible protocols using interface process generation," Proc. of 32nd ACM/IEEE Design Automation Conference, June 1995.

....in the form of parameters such as arbitration priorities, transfer block sizes, etc. Choosing appropriate values for these parameters can significantly impact the latency and transfer bandwidth associated with inter component communication. Finally, there is a body of work on interface synthesis [16, 17, 18, 19, 20, 21, 22, 23], which deals with automatically generating efficient hardware implementations for component to bus or component to component interfaces. These techniques address issues in the implementation of specified protocols, and not in the customization of the protocols themselves. In summary, we believe ....

S. Narayanan and D. D. Gajski, "Interfacing incompatible protocols using interface process generation," in Proc. Design Automation Conf., pp. 468--473, June 1995.

....in [33] which was heuristically generated. Interface process generation also referred to as interface synthesis is the task of automatically generating an interface process between incompatible protocols. There have been several attempts for the automatic generation of interface processes [7, 21, 12, 34, 3, 9] the starting point being the pioneering work by Borriello for automatic transducer synthesis [9] In this work, timing diagrams of the two custom hardware was presented as input and the system produced the logic speci cation of the required glue logic automatically. However this approach did not ....

....the two custom hardware was presented as input and the system produced the logic speci cation of the required glue logic automatically. However this approach did not handle data width mismatches between the two incompatible hardware. This limitation was overcome in later work by Narayan and Gajski [34]. In this work the behaviours of the two incompatible blocks were represented in a hardware description language [49, 20] and then the algorithm veri ed if the two protocols were duals of each other. If they were not exact duals of each other then necessary extra control signals on either side ....

[Article contains additional citation context not shown here]

S. Narayan and D. d. Gajski. Interfacing incompatible protocols using interface process generation. In 32nd Design automation conference, pages 468-473, 1995.

....method for transforming and optimizing protocols. In [10] Narayan addresses the problem of bus interface generation between two different hardware modules of a partial specification. The focus is to optimize the use of a bus by keeping different point topoint communications on it. As described in [11,12], Lin and Narayan consider the problem of interface synthesis with automatic protocol conversion with one or both sides having a fixed interface. In [13] a new design methodology based on interface design was proposed that treated behavior and communication as orthogonal elements. The goal is to ....

....subsystems are adapted, except the interfaces of the IP blocks, according to the implementation selected and interconnected. The interfaces of the IP blocks are connected with the interface connectors of the communication unit. An approach for interfacing incompatible protocols is presented in [11]. The result of interface mapping is a set of interconnected processors communicating through signals, buses and an additional dedicated component (control unit) that establishes the communication of inter processors and adapts protocols when necessary. With this approach it is possible to map the ....

S. Narayan and D. Gajski, "Interfacing Incompatible Protocols Using Interface Process Generation", in Proc. of the IEEE Design Automation Conference, pp.157-164, 1995.

....In [5] 30] Chou and Srivastava use a set of predefined interconnection models during communication synthesis. Several works on protocol selection are reported in the software synthesis for distributed systems [29] Lots of previous work has focused on interface synthesis [6] 8] 21] 22] 26] [27] [28] and [35] In [6] Ecker presents a method for transforming and optimising protocols. In [26] Narayan addresses the problem of bus interface generation between two different hardware mod1 ules of a partitioned specification. The focus is to optimise the bus utilisation by interleaving ....

....and optimising protocols. In [26] Narayan addresses the problem of bus interface generation between two different hardware mod1 ules of a partitioned specification. The focus is to optimise the bus utilisation by interleaving different point to point communications on it. As described in [21] [27], Lin and Nayaran consider the problem of interface synthesis with automatic protocol conversion with one or both sides having a fixed interface. Madsen interface synthesis approach [22] consider the problem of interface adaptation between a fixed interface and a communication medium chosen during ....

[Article contains additional citation context not shown here]

S. Narayan, and D. Gajski, Interfacing Incompatible Protocols Using Interface Process Generation, Proceedings of the IEEE Design Automation Conference, pp. 468-473, June 1995.

....of other types of interfaces. Although we present an example showing two components, our tool is not limited to just two. Similarly, though we present processor memory interfaces, our tool is not limited to those. Our work follows from Narayan s Interface Process Generation approach [5]. Given two incompatible protocols, specified as HDL blocks or processes, their approach generates an interface process to enable communication between the two incompatible protocols. Each protocol is expected to be specified using 5 atomic operations, chosen for the ease of constructing their ....

S. Narayan andD.D. Gajski. Interfacing incompatible protocols using interface process generation. In Proceedings of the 32rd Design Automation Conference, pages 468--473, 1995.

....of these approaches, OOCL can be used to encapsulate the communication using send receive primitives, while implementing the protocol, without any modification to the C or VHDL languages. Other related work includes techniques to interface incompatible protocols by generating an interface process [5] or by synthesizing interface hardware [6] Some other works have suggested extensions to existing languages. In this paper, we present details of OOCL routines for one particular protocol, the PC ISA bus, demonstrate their practical use on two examples, and show why some routines in addition to ....

S. Narayan and D. Gajski, "Interfacing incompatible protocols using interface process generation," in Proceedings of the 32nd Design Automation Conference, pp. 468--473, 1995.

....protocols is given at a very low level of abstraction using waveforms. Jane Sun [13] extends the approach by providing a library of components that frees the user from considering lower level details, but doesn t solve the problem we mentioned. A different approach is that taken by Gajski et al. [8]: first, the protocol specification is reduced to the combination of five basic operations (data read write, control read write, time delay) the protocol description is then broken into blocks (called relations) whose execution is guarded by a condition on one of the control wires or by a time ....

....resolved, the interface can translate between different sequencing of the data and no intended behavior must be introduced to describe the interface process. However, we assume that the two communicating parties are driven by the same clock, a limitation that is not present in [3] and in [8]. As we will see later, the two protocols are described using regular expressions. The use of regular expression for hardware description in general and for protocol description in particular is not new and has been already presented in the literature. The grammar based specification employed in ....

S. Narayan and D. D. Gajski. Interfacing incompatible protocols using interface process generation. In Proceedings of the 32 nd Design Automation Conference, pages 468--473, San Francisco, CA, June 12 - 16 1995.

....Simulation versus Interface Process Generation Interface process generation also referred to as interface synthesis is the task of automatically generating an interface process between incompatible protocols. There have been several attempts for the automatic generation of interface processes [3, 13, 6, 22, 2, 4] the starting point being the pioneering work by Borriello for automatic transducer synthesis [4] In this work, timing diagrams of the two custom hardware was presented as input and the system produced the logic specification of the required glue logic automatically. However this approach did not ....

....two custom hardware was presented as input and the system produced the logic specification of the required glue logic automatically. However this approach did not handle data width mismatches between the two incompatible hardware. This limitation was overcome in a later work by Narayan and Gajski [22]. In this work the behaviours of the two incompatible blocks were represented in a hardware description language [25, 12] and then the algorithm verified if the two protocols were duals of each other. If they were not exact duals of each other then necessary extra control signals on either side ....

[Article contains additional citation context not shown here]

S. Narayan and D. d. Gajski. Interfacing incompatible protocols using interface process generation. In 32nd Design automation conference, pages 468--473, 1995.

....same bus protocol are stored in the same link, in the decreasing order of the bus cost. In general, bus cost is determined by bus width, bus delay, and bus protocol. 9.2 Delay Estimation 9.2.1 Bus Transfer Delay There are two types of protocols: blocked protocol and unblocked protocol. Sanjiv [9] introduces the communication delay estimation for unblocked protocol. According to this method, when channel c is mapped to bus b, we compute the communication time of channel c over bus b as BusTime(c, b) Access(c) #Bits(c) W where Access(c) represents the number of times of data ....

....communicates, and Channel(b) is the set of channels that are mapped to b. 9.5 Bus Selection Inequations 9.5.1 Bus Rate Inequations We divide the bus type selection process to two steps. In this first step, we select bus types according to the maximum bus rate and the channel rate. According to [9] AvgChanRate(b) PeakChanRate(b) As shown in formulations described before, in this step, the process of bus type selection for different buses in the interconnection topology are independent to each other. 9.5.2 Design Constraint Inequations In the second step, we select bus types which ....

Sanjiv Narayan and Daniel D. Gajski. Interfacing incompatible protocols using interface process generation. In Proceedings of the Design Automation Conference, pages 468--473, June 1995.

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Sanjiv Narayan and Daniel D. Gajski. Interfacing incompatible protocols using interface process generation. In DAC '95, 1995.

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S. Narayan and D. Gajski, "Interfacing Incompatible Protocols Using Interface Process Generation", in Proc. of the IEEE Design Automation Conference, pp.157-164, 1995.

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S. Narayan, and D. Gajski, Interfacing Incompatible Protocols Using InterfaceProcess Generation, Proceedings of the IEEE Design Automation Conference, pp. 468-473, June 1995.

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S. Narayan and D. Gajski, "Interfacing Incompatible Protocols Using Interface Process Generation", in Proc. of the IEEE Design Automation Conference, pp.157-164, 1995.

No context found.

Sanjiv Narayan and Daniel D. Gajski. Interfacing incompatible protocols using interface process generation. In DAC '95, 1995.

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S. Narayanan and D. D. Gajski, "Interfacing incompatible protocols using interface process generation," in Proc. Design Automation Conf., June 1995, pp. 468--473.

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S. Narayan and D. Gajski, "Interfacing Incompatible Protocols using Interface Process Generation," in Proc. of Design Automation Conference, 1995, pp. 468--473.

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