Pai Chou, Ross B. Ortega, and Gaetano Borriello. Interface co-synthesis techniques for embedded systems. In ICCAD '95, 1995.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....2 Related Work Hardware software partitioning [2, 3] and high level synthesis [4, 5] have received significant attention over the past decade. Interface synthesis techniques have focused on various issues like optimizing the use of external IO pins of micro controllers and minimizing glue logic [6]. However, the use of memory mapping for interface synthesis has not been considered. Furthermore, hardware software co design methodologies that synthesize the hardware component as an ASIC, pay little attention towards optimizing the memory mapping since the amount of logic that can be mapped to ....

P.Chou, R.Ortega, and G.Borriello. Interface co-synthesis techniques for embedded systems. In International Conference on Computer Aided Design, 1995.

....in [33] which was heuristically generated. Interface process generation also referred to as interface synthesis is the task of auto matically generating an interface process between incompatible protocols. There have been several attempts for the automatic generation of interface processes [7, 21, 12, 34, 3, 9] the starting point being the pioneering work by Borriello for automatic transducer synthesis [9] In this work, timing diagrams of the two custom hardware was presented as input and the system produced the logic specification of the required glue logic automatically. However this approach did not ....

P. Chou, R. B. Ortega, and G. Borriello. Interface co-synthesis techniques for embedded systems. In ICCAD, pages 280-287, 1995.

....of a PCNN with Loadable Coefficients , Presented at the VIDYNN 98 Workshop, Stockholm, Sweden, June, 1998. 30] J. berg, P. Ellervee, Revolver: A high performance MIMD architecture for collision free computing , In Proc. of EuroMicro 98, pp. 301 308, Vsters, Sweden, Aug. 25 27, 1998. Theses [31] J. berg, Tuning of JET Transmission Line Antenna System During ICRH , Master s Thesis, Fusion Plasma Physics, Alfvn Laboratory, TRITA ALF 1993 06. 32] J. berg, An Adaptable Environment for Improved High Level Synthesis , Licentiate Thesis, Electronic Systems Design, TRITA ESD 1996 14. 4 ....

....by Vahid and Tauro in [33] In contrast with [34] they use classes of objects to encapsulate the code needed to describe the communication for different target implementations instead of generating it. Chou et al. present a set of techniques for performing hardware software interface synthesis [31]. Software drivers and glue logic are generated from Control Flow Graph (CFG) descriptions of the communication between an embedded processor and its connected peripheral devices, hardware co processors, or communication interfaces while meeting bandwidth and performance requirements. In [32] ....

P. Chou, R. Ortega, G. Borrielo, "Interface co-synthesis techniques for embedded systems ", In Proc. of ICCAD'95, pp. 280-287, 1995.

....busses. Lahiri et al. 17] present a methodology for the design of custom System on Chip communication architectures, which propose the use of dynamic reconfiguration of the communication characteristics, taking into account the needs of the application. III) Recent work on interface synthesis [4], 5] present techniques to formally derive node clusters from interface timing diagrams. These techniques can be used to provide an abstraction of the connectivity and memory module timings in the form of Reservation Tables [15] Our algorithm uses the Reservation Tables [11, 14] for performance ....

P. Chou, R. Ortega, and G. Borriello. Interface co-synthesis techniques for embedded systems. In ICCAD, 1995.

....in the form of parameters such as arbitration priorities, block transfer sizes, etc. Choosing appropriate values for these parameters can significantly impact the latency and transfer bandwidth associated with inter component communication. Finally, there is a body of work on interface synthesis [16, 17, 18, 19, 20, 21, 22, 23], which deals with automatically generating efficient hardware implementations for component to bus or component to component interfaces. These techniques address issues in the implementation of specified protocols, and not in the customization of the protocols themselves. In summary, we believe ....

P. H. Chou, R. B. Ortega, and G. B. Borriello, "Interface co-synthesis techniques for embedded systems," in Proc. Int. Conf. Computer-Aided Design, pp. 280--287, Nov. 1995.

....and singly structured. We refer to this example as Core3. 2.4 Related work While much work has been done on interfacing, to our knowledge none of the literature includes the idea of prefetching. Most interfacing work has focused on automatically synthesizing logic to interface to a bus (e.g. [9][10] synthesizing the bus itself (e.g. 11] or defining a standard bus protocol (e.g. 12] 3. Pre fetching architectures and heuristics 3.1 Architectures In order to implement the pre fetching for each of the above listed combinations of registers, we developed architectures for ....

P. Chou, R.B. Ortega, G. Borriello. Interface Co-Synthesis Techniques for Embedded Systems. International Conference on Computer-Aided Design, pp. 280-287, 1995.

....implementations and uses processes calling remote procedure calls for communication as behavior description. In Cosyma [9] the behavior is written in a superset of C and is automatically partitioned between hardware and software by using a simulated annealing algorithm. Chinook [5] [18] maps a behavioral description of communicating processes on a single or multiprocessor system and generates software drivers and glue logic to connect processors and external chips but not for FPGAs. The SIERA co design framework [19] maps a network of concurrent processes onto a printed ....

P. Chou, R. Ortega, and G. Borriello. Interface co-synthesis techniques for embedded systems. In Proc. of the IEEE/ACM Int. Conf. on CAD (ICCAD), pages 280--287, San Jose, November 1995.

....etc. usedbythechannels buses in the selected topology. The VSI Alliance on chip bus working group [14] has recognized that a multitude of bus protocols will be needed in order to serve the wide range of SOC communication requirements. Finally, there is a body of work on interface synthesis [15, 16, 17, 18, 19, 20, 21, 22], which deals with automatically generating efficient hardware implementations for component to bus or component to component interfaces. These techniques address issues in the implementation of specified protocols, and not in the customization of the protocols themselves. In summary, we believe ....

P. H. Chou, R. B. Ortega, and G. B. Borriello, "Interface co-synthesis techniques for embedded systems," in Proc. Int. Conf. Computer-Aided Design, pp. 280--287, Nov. 1995.

....can easily be extended but it limits performance. Since several software processes can access a single coprocessor, there are potential resource conflicts requiring process synchronization and mutual exclusion. Peripheral resource utilization is an optimization problem and is, e.g. addressed in [19]. 5. Architectures for Data Dominated Systems 5.1. DATA DOMINATED SYSTEMS The term data dominated systems can be used for systems where data transport requirements are dominant for the design process, such as in telecommunication, or where a stream of data shall be processed, such as in digital ....

....and data flow optimization would be a worthwhile topic which goes beyond the work in data dominated systems which has been mentioned above. Related to this problem are communication channel selection and communication optimization. Component interface synthesis is already an active research topic [54, 55, 19]. Specialization for power minimization would clearly be another topic of interest. All problems should be approached under flexibility requirements. On the other hand, the classification of specialization techniques could be applied to support component selection and component reuse. In this ....

Chou, P., Ortega, R., Borriello, G. (1995) Interface Co-Synthesis Techniques for Embedded Systems. Proc. ICCAD 95, 280-287.

....such as that performed in [GaGl96] has investigated specifying and scheduling communication between hardware and software subsystems. The research presented here focuses on generating a low level, synthesizable description of synchronous interfaces between hardware components. Similarly, [ChOrBo95] describes a mechanism for creating the glue logic between two hardware components, but requires a functional description of component ports. In this paper, we present the POLARIS tool, which converts a subsystem s communication protocol into a standard scheme given an HDL description of the ....

....the client receive buffer. If the resource datapath is thinner than the client datapath, an Acknowledge is returned to the client interface when the resource register is filled. Address extraction is currently a manual task. It can be performed using a simplified version of the structures that ([ChOrBo95], MaHa95] used to achieve interface synthesis. These two employed structures called signal sequences (SEQs) and protocol flow graphs (PFGs) respectively, to model the bit patterns that are required to interact with a component. In the case of POLARIS, a sequence of higher level descriptions ....

Pai Chou, Ross B. Ortega, Gaetano Borriello, "Interface Co-Synthesis Techniques for Embedded Systems", Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp.280-287, 1995.

....core pipeline timing and the storage elements timings, allowing for faster DSE iterations. To our knowledge no previous compiler can exploit detailed timing information of efficient memory access modes offered by modern DRAM libraries (e.g. SDRAM, RAMBUS) Recent work on interface synthesis [2], 3] present techniques to formally derive node clusters from interface timing diagrams. These techniques can be applied to provide an abstraction of the memory module timings required by our algorithm. Our technique generates accurate operation timing information by marrying the pipeline timing ....

P. Chou, R. Ortega, and G. Borriello. Interface co-synthesis techniques for embedded systems. In ICCAD, 1995.

....analysis techniques presented in [17] 25] to recognize and isolate the cache misses in the compiler, and then schedule them to better hide the latency of the misses. III. Additional related work addresses extraction and utilization of accurate memory timing in the context of interface synthesis [4], 5] hardware synthesis [16] 22] and memoryaware compilation [9] Ly et al. 16] use behavioral templates to model complex operations in a CDFG. Panda et al. 22] present a pre synthesis approach to exploit efficient access DRAM modes. 9] presents an approach to marry the timing of memory ....

P. Chou, R. Ortega, and G. Borriello. Interface co-synthesis techniques for embedded systems. In ICCAD, 1995.

....The row and column addresses are available at the first and second stages respectively, and the output data is available at the beginning of the third stage. Techniques for formally deriving the node clusters from interface timing diagrams have been studied in the interface synthesis works such as [4], and can be applied in this context. Assuming a clock cycle of 15 ns, and a 1 cycle delay for the addition and shift operations, we 6 derive the schedule shown in Figure 3(b) for the code in Figure 3(a) using the memory read model in Figure 2(b) Since the 2 Theta 16 accesses to arrays x and ....

P. Chou, R. Ortega, and G. Borriello. Interface co-synthesis techniques for embedded systems. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pages 280--287, November 1995.

....implementations and uses processes calling remote procedure calls for communication as behavior description. In Cosyma [9] the behavior is written in C x a superset of C and is automatically partitioned between hardware and software by using a simulated annealing algorithm. Chinook [5] [18] maps a behavioral description of communicating processes on a single or multiprocessor system and generates software drivers and glue logic to connect processors and external chips but not for FPGAs. The SIERA co design framework [19] maps a network of concurrent processes onto a printed ....

P. Chou, R. Ortega, and G. Borriello. Interface co-synthesis techniques for embedded systems. In Proc. of the IEEE/ACM Int. Conf. on CAD (ICCAD), pages 280--287, San Jose, November 1995.

....in the form of parameters such as arbitration priorities, transfer block sizes, etc. Choosing appropriate values for these parameters can significantly impact the latency and transfer bandwidth associated with inter component communication. Finally, there is a body of work on interface synthesis [16, 17, 18, 19, 20, 21, 22, 23], which deals with automatically generating efficient hardware implementations for component to bus or component to component interfaces. These techniques address issues in the implementation of specified protocols, and not in the customization of the protocols themselves. In summary, we believe ....

P. Chou, R. B. Ortega, and G. Borriello, "Interface co-synthesis techniques for embedded systems," in Proc. Int. Conf. Computer-Aided Design, pp. 280--287, Nov. 1995.

No context found.

P. Chou, R. Ortega, and G. Borriello. Interface co-synthesis techniques for embedded systems. In Proc. International Conference on Computer-Aided Design, pages 280--287, 1995.

....5 Software Architecture Synthesis The software architecture can be synthesized from a system (hardware) architecture model, the modes of the system, and user code organized in objects. The architecture model instantiates the devices and interconnection schemes for device driver synthesis [4, 5]. The compilation is done in two phases: one to compile and run the CAD tool for static scheduling and generate code for the customized run time system, and the second to build the custom OS with the user code. 5.1 Input Data Structures The user describes modes by supplying the mapping function ....

P. Chou, R. Ortega, G. Borriello, "Interface Co-Synthesis Techniques for EmbeddedSystems," in Proc. ICCAD, 1995. pp. 280287.

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Pai Chou, Ross B. Ortega, and Gaetano Borriello. Interface co-synthesis techniques for embedded systems. In ICCAD '95, 1995.

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P. Chou, R. B. Ortega, and G. Borriello. Interface cosynthesis techniques for embedded systems. In Proc. of ICCAD, 1995.

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P. Chou, R. Ortega, G. Borriello. Interface co-synthesis techniques for embedded systems. ICCAD, 1995.

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P. Chou, et al. Interface co-synthesis techniques for embedded systems. ICCAD, 1995.

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Pai Chou, Ross B. Ortega, and Gaetano Borriello. Interface co-synthesis techniques for embedded systems. In ICCAD '95, 1995.

No context found.

P. H. Chou, R. B. Ortega, and G. B. Borriello, "Interface co-synthesis techniques for embedded systems," in Proc. Int. Conf. Computer-Aided Design, Nov. 1995, pp. 280--287.

No context found.

P. Chou, R. Ortega, and G. Borriello, "Interface Co-Synthesis Techniques for Embedded Systems," in Proc. of International Conference on Computer-Aided Design, 1995, pp. 280-- 287.

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P. Chou, R. Ortega, G. Boriello. "Interface Co-synthesis Techniques for Embedded Systems". In Proceedings of the International Conference on Computer-Aided Design, 1995.

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