J. S. Lis and D. D. Gajski, "Synthesis from VHDL," in Proceedings of the International Conference on Computer Design, 1988, pp. 378--381.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... problem of checking the consistency of a specification with timing constraints has been addressed, for instance, in [3] 11] 13] Instead, concerning the use of VHDL as specification language for synthesis, the problem of defining a synthesizable subset of the whole language has been addressed in [12] [9] 4] 14] 7] 8] In pure VHDL, the typical algorithmic constructs, composed by high level sequential statements, can be specified using processes, functions and procedures, whereas the timing behavior of a process is determined by signals and wait statements. As the language simulation ....

J. Lis, D. Gajski, "Synthesis from VHDL", Proceedings of ICCD, October 1988.

....to many existing professional tools for design synthesis and simulation. Again, because of this complexity, the field of high level synthesis (HLS) has recently emerged to address the need for design methods and techniques at the RTL level. Currently there are several such tools that have appeared [9, 18, 6], but the HLS area is not mature yet [5] Just as with the design, the test process, particularly test generation, has matured at the logic gate and circuit levels. For example, there are several tools for test generation, including some recent ones based on logic synthesis techniques [1] ....

J. Lis, D. Gajski, "Synthesis from VHDL," Inter. Conf. on Computer Design, 1988, pp. 378-381.

....regarding the type, parameters, ports and functionality of the components under them. The component library is supplemented by query routines, performance metric routines, behavioral model, synthesis model and gate count generators. An application C program such as High level Synthesis tool (e.g. [LiGa88][RaGa91] interacts with GENUS by assigning a component s parameter values. The GENUS library uses these parameters to initially create a component and delete the component when necessary. GENUS also provides query routines to retrieve an instantiated component s attributes (e.g. port information, ....

J. S. Lis and D. D. Gajski, "Synthesis from VHDL," Proc. IEEE Int. Conf. on Computer Design, pp378-381, 1988.

....describes the estimation models we have developed. Section 5 describes the experiments performed to validate our models. We show that our models are simple, fast and provide fairly accurate results (within 10 of actual values) Furthermore, the estimators are integrated with an existing HLS system[LiGa88] and run on line during the tasks of component selection and allocation. Section 6 concludes with a summary. 2 Related Work The problem of area and delay estimation has been studied at several design levels and in several contexts. At the level of a complete datapath design, work has been done to ....

....the estimation technique on both combinational and sequential RT components. The experiments show very good results, with aggregate errors in the range of 610 . Our area delay models are simple, fast and fairly accurate, and have been integrated with an existing high level synthesis system [LiGa88] [RaGa91] Although our experiments were based on area delay values generated by previously benchmarked tools and not by actual layouts, we believe that the estimation approach we presented is general and that it can produce even better results if provided with more accurate sample design data ....

J. S. Lis and D. D. Gajski, "Synthesis from VHDL," Proc. IEEE Int. Conf. on Computer Design'88, pp.378-381, 1988.

....the most popular approach for a more general class of circuits. The IEEE standard VHDL for example was specifically designed for flexibility (see [2] for a complete overview) and is now the foundation of continued research and development in synthesis, for several levels of design specification [3,4,5] Current research in design automation at the University of South Florida uses USF s hardware design language FHDL as the specification language for an integrated circuit synthesis tool [6] One desirable feature of any design specification technique is that it be easy to use, especially ....

Lis, Joseph S., Daniel D. Gajski, "Synthesis From VHDL", IEEE Int. Conf. on Computer Design, 1988, pp.378-381.

....loops combined with explicit synchronization statement (wait) control statements (if, case) and exceptions (EXIT) it provides restricted facilities for data flow analysis and transformations. 3.4.3. Control Data Flow Graph (CDFG) This model extends DFG with control nodes (If, case, loops) [26]. This model is very suited for the representation of data flow oriented applications. Several codesign tools use CDFG as intermediate form [4] Lycos, Vilcar] 3.5 ARCHITECTURE ORIENTED INTERMEDIATE FORMS This kind of intermediate form is closer to the architecture produced by codesign than to ....

J.S. Lis and D.D. Gajski. Synthesis from VHDL. In Proceedings of the International Conference on Computer-Aided Design, pages 378--381, October 1988.

....we discuss our approach to the estimation problem. Section 4 describes the experiments performed to validate our models. We show that our models are simple, fast and provide fairly accurate results (within 10 of actual values) Furthermore, the estimators are integrated with an existing HLS system[16] and run on line during the tasks of component selection and allocation. Section 5 concludes with a summary. 2 Related Work The problem of area and delay estimation has been studied at several design levels and in several contexts. At the level of a complete datapath design, work has been done ....

....the estimation technique on both combinational and sequential RT components. The experiments show very good results, with aggregate errors in the range of Sigma10 . Our areadelay models are simple, fast and fairly accurate, and have been integrated with an existing high level synthesis system [16] [20] Although our experiments were based on area delay values generated by previously benchmarked tools and not by actual layouts, we believe that the estimation approach we presented is general and that it can produce even better results if provided with more accurate sample design data points. ....

J. Lis and D. Gajski, "Synthesis from VHDL," Proc. IEEE Int. Conf. on Computer Design'88, pp.378-381, 1988.

....of sequence edges to denote the sequential ordering of operations as found in a (procedural) input language [Brayton88] 2. 3 Separation of data and control flow Many systems limit the data flow analysis to so called straight line code only, generating several blocks with data flow code [Lis88, Pangrle87]. Conditional constructs, loops, and procedure calls are represented in a separate control graph. Although relatively easy to implement, this again severely limits many algorithms (graph optimizations, scheduling, allocation) in their search space, increasing the risk of staying with suboptimal ....

LIS, J.S. AND D.D. GAJSKI, "Synthesis from VHDL," in Proc. of the IEEE International Conference on Computer Design 1988 , pp. 378--381, 1988.

.... and the physical design level are as follows: Microarchitecture Level : Although numerous hardware description languages have been developed, our optimization methods work on a language independent intermediate representation called the disjoint control and data flow graph (CDFG) [13, 11]. The rationale behind such a design decision is: enable integration with (i) existing hardware description languages and of course (ii) the still evolving hardware description language standards. The performance is measured as the number of clock cycles times the duration of each clock cycle ....

J. S. Lis and D.D. Gajski. Synthesis from VHDL. In Proceedings of the International Conference on Computer Design, pages 378--381, 1988.

.... reduce the workload of the designer, the tasks of module allocation, partitioning, and refinement can be automated by various tools [12, 13, 14] Once the system modules have been completely specified as a result of system design tasks, we can use software generators and hardware design compilers [15, 16] to obtain a software hardware implementation of each module. By capturing desired functionality with an executable specification language and using automated estimators, the disadvantages of the current methodology are overcome. 6 Specification Language Estimators, Simulation concept system ....

J. Lis and D. Gajski, "Synthesis from VHDL," in Proceedings of the International Conference on Computer Design, 1988.

....unique internal representation can tremendously simplify the use of the synthesis system because users can describe the functionality of the intended design with any language constructs or writting styles and still obtaining the same synthesized hardware. Traditional representations, such as CDFG [10, 12], VT [11] and CF DFG [3] satisfy the completeness property by encoding the input description into the representation in a one to one mapping manner. In other words, each language construct in the description is realized with a particular topology of nodes in the representation. For example, a ....

....each language construct in the description is realized with a particular topology of nodes in the representation. For example, a VHDL[18] description can be compiled into a CDFG by mapping computations in a basic block to nodes in a data flow graph, and a conditional constructs to a control nodes [10, 12]. Similar mappings from VHDL to CFG and from ISPS [1] to VT can be found in [3, 4, 11, 16] Although these representations shown to be efficient, they lack the uniqueness. Since there exists a one to one correspondence between the constructs of input descriptions and the schema for the internal ....

J.S. Lis and D.D. Gajski, "Synthesis from VHDL," Proc. IEEE Int. Conf. on Computer Design'88, pp.378-381, 1988.

....loops) that make use of complex data types, e.g. integers, arrays, and records) Most systems synthesize designs from such descriptions by associating each language construct with a particular hardware structure. For example, conditional branches and loops are translated to control structures [5, 7, 9, 14], while operations in basic blocks are executed in a datapath [7, 12] Because of the close relationship between language constructs and the synthesis algorithms the design quality obtained from these systems is dependent on the input description. In other words, semantically equivalent ....

....dependent on the input description. In other words, semantically equivalent descriptions that differ syntactically could result in distinctively different designs. Let us consider systems, which evaluate conditions of a branch statement in the control step that precedes operations in the branches [5, 7, 9, 14, 18]. Results generated by these systems depend on the way conditional branches are ordered or grouped in the input description. For example, Figure 1(a) shows two descriptions that have the same semantics but different ordering of conditional branches. When scheduling Description1 and Description2 ....

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J.S. Lis and D.D. Gajski, "Synthesis from VHDL," Proc. IEEE Int. Conf. on Computer Design'88, pp.378-381, 1988.

.... 01 s3 s0 010100010 00 s2 s3 100101000 01 s2 s3 101000100 10 s2 s0 010100010 s4 s0 101000010 s0 s1 101000001 s1 s2 100100010 Figure 8: Scheduling Results 14 5 Experiments and Results We have incorporated our architecture based synthesis methodology into our VHDL Synthesis System (VSS) [6,12] which is fully implemented in C language running on a Sparc Workstation. We have tested this architecture based synthesis methodology on a wide range of examples. In this section we use five different examples to show the relationship between architecturalspecification and synthesis. These ....

J.S. Lis and D.D. Gajski, "Synthesis from VHDL," Proc. IEEE Int. Conf. on Computer Design'88, pp.378-381, 1988.

....Implementation In order to implement the design in hardware, for each VHDL process, an RT block structure must be defined which should be capable of performing the computations specified in that process. This is achieved by using a VHDL synthesis tool such as the VHDL Synthesis System (VSS) [5, 6, 7]. VSS takes a VHDL description as an input. Given a resource constraint (such as the maximum number of adders that can be used) VSS schedules operations in the description to maximize the system performance. Alternatively, given a performance constraint, VSS will attempt to schedule the ....

J. Lis and D. Gajski, "Synthesis from VHDL," in Proc. of the ICCD, 1988.

....not necessarily suitable for high level synthesis. Given that both functional and behavioral abstractions are appropriate for describing certain types of designs, a production quality synthesis system must handle both in order to be a useful tool. Figure 2 shows the relationship between high level [15, 9, 12, 20], functional, and logic level synthesis [1, 6] High level synthesis maps a behavioral description of the desired system to a RTL structure of generic components [15, 20] Functional synthesis synthesizes a functional description of one or possibly several RTL components to component(s) from a ....

.... 0001 when 11 ; entity design1 is port (F : in BIT VECTOR(1 downto 0) D : out BIT VECTOR(3 downto 0) architecture design1 body of design1 is begin (b) Partitioned ECDFG. d) Maximally Merged ECDFG. c) Reduced ECDFG. Figure 5: FSA on the Adder Subtracter Design Example. 1) A language compiler [9] parses the input description, a functional description, into an internal ECDFG design representation [18] Examples of both are given in Figures 5(a) and 5(b) respectively. 2) The functionality recognizer addresses the mismatch problem between the standard operators of the language and the ....

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J. S. Lis and D. D. Gajski, Synthesis from VHDL, ICCD, pp. 378--381, 1988.

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J. S. Lis and D. D. Gajski, "Synthesis from VHDL," in Proceedings of the International Conference on Computer Design, 1988, pp. 378--381.

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