L. Guerra, M. Potkonjak, and J. Rabaey, "High level synthesis for reconfigurable datapath structures," in Proc. Int. Conf. Computer-Aided Design, Nov. 1993, pp. 26-29.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....fault tolerance suffers a performance loss due to longer detection recovery time. High level synthesis has been well explored [GDWL92] Lately progress has been made towards the incorporation of more sophisticated design constraints such as power [GOC94] testability [HO94] and fault tolerance [KO94, OK94, KO93, GPR93]. Fault tolerance has been incorporated on the chip level by techniques such as self recovery [KO94] replication [OK94, KO93] and Built in Self Repair [GPR93] KO94, OK94, KO93] perform scheduling as an initial attempt to incorporate on chip faulttolerance through the use of high level synthesis ....

.... the incorporation of more sophisticated design constraints such as power [GOC94] testability [HO94] and fault tolerance [KO94, OK94, KO93, GPR93] Fault tolerance has been incorporated on the chip level by techniques such as self recovery [KO94] replication [OK94, KO93] and Built in Self Repair [GPR93]. KO94, OK94, KO93] perform scheduling as an initial attempt to incorporate on chip faulttolerance through the use of high level synthesis design methodology. KO94] reschedules the second copy to take advantage of load balancing to minimize the area overhead due to fault tolerance and [OK94] ....

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L. Guerra, M. Potkonjak, J. Rabaey. High Level Synthesis for Reconfigurable Datapath Structures. In ICCAD, pages 26--29, November 1993.

....for area optimization using rephasing. The only modification is the inclusion of CDFG duplication as a preprocessing step. An efficient BISR (Build In Self Repair) fault tolerance technique based on exploiting the flexibility provided by design space exploration has been proposed recently [Gue93]. BISR is a widely used technique for yield and permanent fault tolerance enhancement where in addition to operational modules, a set of spare module is also provided. If a faulty module is detected, it is replaced with a spare module. The main idea in the high level synthesis BISR technique is to ....

L. Guerra et al. "High Level Synthesis for Reconfigurable Datapath Synthesis", ICCAD-93, pp. 26-29, 1993.

....all of these fault tolerant VLSI Systems are manually designed. In contrast, in this paper we will outline computer aided design techniques for rapidly designing area efficient fault tolerant VLSI systems. Related research in this area includes automatic incorporation of built in self repair (BISR)[5] and checkpoint insertion[17] Towards this end we will first outline the computer aided design methodology for fault tolerant VLSICs in section 2. This will be followed by a detailed description of self recovering and reliable VLSIC synthesis in sections 3 and 4. In section 5, the fault tolerance ....

....can be approximated as the product of the reliabilities of the components in its module set. Let R sys be the desired system reliability and let R 1 i , R 2 i , R n i i be the reliabilities of the n i modules of the i th type. These can be computed using the formula for reliability [5] as follows. The reliability of an N modular redundant (NMR) 16 Module Name Reliability Adder 0.995 Multiplier 0.980 Register 0.9975 Multiplexer 0.9975 Majority Voter 0.9975 Table 3: Module Reliabilities system is RNMR = P n i=m n i R i Theta (1 Gamma R) n Gammai where R is the ....

L.M. Guerra, M. M. Potkonjak, and J. M. Rabaey. High Level Synthesis for Reconfigurable Datapath Structures. In Proceedings of 1993 IEEE International Conference on Computer Aided Design, pages 26--29, 1993. 25

....has significantly higher impact on the quality of the final implementation than other high level synthesis tasks, like scheduling and assignment. Techniques using transformations to optimize area [33] throughput [32] throughput and latency [36] power [5] and transient [19] and permanent [16] fault tolerance report Manuscript received September 1, 1994; revised January 25, 1995. This paper was recommended by Guest Editors W. Maly and Y. Zorian. The authors are with C C Research Laboratories, NEC USA, Princeton, NJ 08540 USA. IEEE Log Nmnber 9410364. improvements between factor of ....

L. Guerra, M. Potkonjak, and J. Rabaey, "High level synthesis for reconfigurable datapath structures," in Proc. Int. Conf. Computer-Aided Design, Nov. 1993, pp. 26-29.

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L. Guerra, M. Potkonjak, and J. Rabaey, "High level synthesis for reconfigurable datapath synthesis," in Proc. ICCAD-93, 1993, pp. 26--29.

....VLSI algorithms, parallel algorithms, logic synthesis, and computer architecture. Transformations have been successfully used in high level synthesis for optimization of variety of goals, including area, throughput, latency, power, and Iransient and permanent fault tolerance. 201, 24] 3] 10] 21] Recently, a new wansformation technique was developed which increases the com plexity of the behavioral description while reducing the structural complexity of the resulting datapath [9] Application of the new transformation technique, hnt potato, to reduce the partial scan overhead ....

....required for a given frequency response, for a sampling rate of 580ns. None of the different filter implementations were originally testable. Table 1 shows the number of scan flip flops (FFs) required by BETS [8] a behavioral test synthesis system, to make the corresponding implementations 100 testable. BETS provides algorithms which support testability optimization during resource allocation, scheduling and assignment. BETS targets simultaneously both resource utilization (i.e. area for a given timing constraints) and testability. In all cases a significant test hardware overhead ....

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L. Guerra, M. Potkonjak, J. Rabaey: "High Level Synthesis for Reconfigurable Datapath Structures", ICCAD93, pp. 26-29, November 1993.

....partitioning techniques were pioneered by McFarland [McF83] and Camposano and Brayton [Cam87] Lagnese and Thomas [Lag89] generalized this work by considering multi stage clustering and reported 20 reduction in the number of wiring tracks on a benchmark example. Recently, synthesis of ASPPs [Gue93] and ASIPs [Leu94, Goo95] received a great deal of attention in CAD community. While both ASPPs ASIPs and the technique proposed in this paper target implementation of several tasks on the same processor, the similarity between two domains is very limited. For example, while both ASIP and ASPP ....

L. Guerra, M. Potkonjak, J. Rabaey, "High Level Synthesis for Reconfigurable Datapath Structures", ICCAD93, pp. 26-29, 1993.

....algorithms, we have applied them on several benchmark designs. The examples were collected from the following technical manuscripts: eighth order continued fraction IIR filter, linear GE controller, Volterra filters, long echo canceler, wavelet filter, modem filter, Motorola C133 filter [8], 16] 17] and a real life avionics VTSOL controller [10] For all experiments, HYPER was used as a behavioral compiler to obtain register transfer level (RTL) implementations [17] Design for debugging analysis was performed to determine the cuts and the extra hardware overhead needed to ....

L. Guerra, M. Potkonjak, and J. Rabaey, "High level synthesis for reconfigurable datapath structures," in Proc. Int. Conf. Computer-Aided Design, 1993, pp. 26--29.

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L. Guerra, M. Potkonjak, and J. Rabaey. High Level Synthesis for Reconfigurable Datapath Structures. International Conference on Computer-Aided Design, pp. 26-29, 1993.

.... however, it was realized that the scheduling in the traditional behavioral synthesis usually does not have high impact on the quality of the final implementation [49] and that other synthesis optimization tasks, such as transformations, usually make greater differences in the final results [5] [16] [22] 32] 33] Moreover, it was reported that the available scheduling algorithms often produce optimal results [6] 36] 39] The focus of behavioral synthesis research, therefore, shifted from scheduling to other issues of synthesis that were found to be 3 more beneficial if addressed. From ....

L. Guerra, M. Potkonjak, and J. Rabaey. High-level synthesis for reconfigurable datapath structures. In Proceedings of ICCAD '93, Santa Clara, CA, 1993. Intl. Conf. Computer-Aided Design. 29

....experimentation. While the initial application of transformations in high level synthesis was mainly based on the use of compiler like strategies [McF92] recently emphasis has been shifted to target statistically validated objective functions which model area [Pot92] fault tolerance overhead [Gue93] and power [Cha92] Transformations used in all domains are mainly based on a very few common principles. All currently used syntax transformations can be classified into three groups: control flow transformations, transformations for alternation of the organization of computations and dataflow ....

L. Guerra, M. Potkonjak, J. Rabaey: "High Level Synthesis for Reconfigurable Datapath Structures", ICCAD93, pp. 26-29, November 1993.

....VLSI algorithms, parallel algorithms, logic synthesis, and computer architecture. Transformations have been successfully used in high level synthesis for optimization of variety of goals, including area, throughput, latency, power, and transient and permanent fault tolerance. 20] 24] 3] [10], 21] Recently, a new transformation technique was developed which increases the complexity of the behavioral description while reducing the structural complexity of the resulting datapath [9] Application of the new transformation technique, hot potato, to reduce the partial scan overhead for ....

L. Guerra, M. Potkonjak, J. Rabaey: "High Level Synthesis for Reconfigurable Datapath Structures", ICCAD93, pp. 26-29, November 1993.

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