S. Kimura, T. Igaki, H. Haneda. "Parallel Binary Decision Diagram Manipulation." In IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E75-A, No. 10, pp 1255-62, October 1992.  Home/Search   Document Not in Database   Summary   Related Articles

....combining resources, applications can take advantage of both more memory and more processing power. Such networks of workstations are common in the engineering workplace. 2 To date, parallel BDD implementations that have been developed include packages for shared memory multi processor systems [2], for a distributed shared memory (DSM) platform [1] for SIMD architectures [10] and for vector processors [11] In a shared memory multi processor system, multiple processors share the same physical memory. Contention for shared memory is handled by semaphores and locks. While this method is ....

....for a particular network topology, the results obtained from our implementation of this model on the Meiko CS 2 are promising. Often, parallelism may be extracted from a particular algorithm in several different ways. For instance, 10] explores parallelism in breadth first BDD traversals [12] In [2], parallelism in operation sequences is examined. This thesis describes techniques that allow several different forms of parallelism to be exploited in depthfirst algorithms on a distributed BDD data structure. For instance, the BDD structure is stored in a distributed hash table and can be ....

S. Kimura, T. Igaki, H. Haneda. "Parallel Binary Decision Diagram Manipulation." In IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E75-A, No. 10, pp 1255-62, October 1992.

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