B. A. Gennart and D. C. Luckham. Validating discrete event simulations using event pattern mappings. In DAC '92: Proceedings of the 29th ACM/IEEE conference on Design automation, pages 414--419, Los Alamitos, CA, USA, 1992. IEEE Computer Society Press.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....environments for ASICs may have test cases written in terms of bus transactions. The translation process views a high level operation as a long sequence of low level state transitions that drive the IUT along the high level test execution path. This is done by means of pattern matching, as in [6]. Essentially, a parser follows the state transitions and generates a high level operation (e.g. transaction) whenever it recognizes a pattern that indicates that such a transaction is taking place. The sequence of high level operations thus recognized is a skeleton for concrete test. More ....

A. Benoit and D. Luckham. Validating Discrete Event Simulations Using Event Pattern Mappings. In ACM/IEEE Design Automation Conference, pages 414--419, 1992.

....We translate a FSM transition path into a concrete system test sequence that can be applied in the simulation environment, in the form of processor assembly programs. There has been work on pattern mapping between different levels of simulation, mapping low level events to upper level operations [35]. However, the designer must provide all the mapping relationship in the VAL language, which is effective as an assertion checker for a small number of operations in a simulation trace. We use a more general pattern matching mechanism to recognize the system level operations (instructions) and ....

B. Gennart and D. Luckham. Validating Discrete Event Simulations Using Event Pattern Mappings. In Proc. of the Design Automation Conf., pages 414-- 419, 1992.

....uses separate user defined specifications associated with VHDL architectures, and checks during the simulation to see if the specifications are consistent with the simulation results. But the specifications are not part of the design, which needs additional designer efforts. Event pattern mapping[3] is another verification method based on simulation results. In this method, the designer specifies an event pattern in high level simulation and the corresponding event pattern consisting of several events in low level simulation, and the debugger checks the agreement of the two event patterns by ....

B. A. Gennart and D. C. Luckham, "Validating discrete event simulations using event pattern mappings," Proc. of the 29th Design Automation Conference, pp. 414-419, 1992.

....in views that leaves a family of models (or framework) for testing DTP standards. Each view is a reference architecture that is formally defined and may be simulated, animated, and related to other views. iv This dissertation also applies a technique developed previously by Gennart and Luckham [28] for testing applications for conformance with reference architectures. This technique is based upon pattern mappings. Pattern mappings specify relationships between architectures, and they permit an application s execution to be automatically runtime tested for conformance with the constraints of ....

.... domain, ffl a reference architecture for the X Open DTP industry standard, ffl an extension to the X Open reference architecture to specify isolation, and ffl an application of a methodology for testing applications for conformance to reference architectures developed by Gennart and Luckham [28]. 1.4.1 Domain of DTP This dissertation develops concepts and language for formally defining the domain of DTP. A domain is a set of concepts, predicates, components, protocols, and architectures. The domain of DTP presented includes a collection of basic and predefined types for formally ....

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Benoit A. Gennart and David C. Luckham. Validating discrete event simulations using event pattern mappings. In Proceedings of the 29th Design Automation Conference (DAC), pages 414--419, Anaheim, CA, June 1992. IEEE Computer Society Press.

....simulation real time systems. In the DRTSS framework, the output analysis system detects patterns of events, computes statistics based on data generated when a pattern is detected, and exercises run length control over the execution engine. The need for features similar to these is argued for in [27] and [52] Hierarchical simulation is rarely addressed in simulation environments designed for realtime systems. Hierarchical simulation is, however, used in other fields such as integrated circuit design. There are two areas of simulator technology research that are orthogonal to the above ....

....An output variable contains a compound event specification, given in a language called CELL, that is matched against the stream of events generated when the simulation is run. When the specification is satisfied, the output variable triggers and a simulationist specified event is generated. In [27], Gennart and Luckham describe a similar approach based on a language called VAL , which is an extension to the hardware description language VHDL. Gennart and Luckham argue that examining the low level event stream generated by a hardware simulator is tedious, error prone, and not interesting. We ....

B. A. Gennart and D. C. Luckham. Validating discrete event simulations using event pattern mappings. In Proceedings. 29th ACM/IEEE Design Automation Conference, pages 414--19, June 1992.

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B. A. Gennart and David C. Luckham. Validating discrete event simulations using event pattern mappings. In Proc. 29th Design Automation Conference (DAC), Anaheim, Hune 1992, pp. 414-419, IEEE Computer Society Press.

....bottlenecks. These characteristics, as presented in the Rapide language, have been used to build an executable standard for the SPARC V9 instruction set architecture[SPL95] One other great advantage of computations is that one can use maps to build new computations in order to validate systems[GL92] Mel90] Maps are objects that take computations as inputs and produce computations as output. Maps look for specific event patterns in the input computation and when a match is found add events to the output computation. Parameter values from the pattern match may be used in the creation of the ....

Benoit A. Gennart and David C. Luckham. Validating discrete event simulations using event pattern mappings. In Proceedings of the 29th Design Automation Conference (DAC), pages 414--419, Anaheim, CA, June 1992. IEEE Computer Society Press, Best paper award.

....as its bottlenecks. These characteristics, as presented in the Rapide language, have been used to build an executable standard for the SPARC V9 instruction set architecture[14] One other great advantage of computations is that one can use maps to build new computations in order to validate systems[2][11] Maps are objects that take computations as inputs and produce computations as output. Maps look for specific event patterns in the input computation and when a match is found add events to the output computation. Parameter values from the pattern match may be used in the creation of the ....

GENNART, B. A., AND LUCKHAM, D. C. Validating discrete event simulations using event pattern mappings. In Proceedings of the 29th Design Automation Conference (DAC) (Anaheim, CA, June 1992), IEEE Computer Society Press, pp. 414--419.

....into sections describing the underlying poset model and concepts followed by an outline of Rapide with examples of components, architectures and mappings. Application of these concepts, particularly refinement maps, to hardware designs in the event based simulation language VHDL was presented in [6]. 2 Example Architectures We illustrate our concepts using examples of simple system architectures. We start with the usual informal pictures. The first example is a HiFi system described at a level of detail in which the components are familiar to all buyers. Figure 1 shows such a system ....

....been refined into subarchitectures of A) Refinement is a transitive relation between architectures, and is, generally speaking, the relationship that exists between architectures for the same system at different levels of abstraction in a design hierarchy. Experiments using VAL VHDL reported in [6] demonstrate that refinement maps are a powerful tool for controlling the complexity of the output from large simulations and for locating errors in large low level designs. Definition. A binding of an architecture A to an interface I is a pair of (1 1) mappings, M in and M out such that (i) M ....

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Benoit A. Gennart and David C. Luckham. Validating discrete event simulations using event pattern mappings. In Proceedings of the 29th Design Automation Conference (DAC), pages 414--419, Anaheim, CA, June 1992. IEEE Computer Society Press.

....in one architecture into posets in another. This is a powerful feature for relating architectures which may possibly differ widely so that, e.g. many sets of events in one might correspond to a single event in the other. Event pattern mappings were first used experimentally on VHDL simulations in [14]. D. Issues One of software architecture s major goals is to enable the construction of very large system architectures. Scalability is obviously of prime importance. For example, ffl large numbers of connections, ffl dynamic creation of components and dynamically selectable connections, ffl ....

....architecture features of Rapide, not the general reactive programming features, we will not describe the executable language further. The reader is referred to [2] and [4] for more information. E. Pattern Language The concept of event patterns is similar to that developed in [27] 28] 29] [14]. Event patterns define subsets of poset computations. Patterns may be constructed using the following syntax: pattern : basic pattern j pattern binary pattern operator pattern j pattern ( iterator operator binary pattern operator ) j pattern where guard j f placeholder decl g ....

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Benoit A. Gennart and David C. Luckham, "Validating discrete event simulations using event pattern mappings", in Proceedings of the 29th Design Automation Conference (DAC), Anaheim, CA, June 1992, pp. 414--419, IEEE Computer Society Press.

....This section gives an example of two Rapide architectures for a simple microprocessor and an event pattern mapping from one to the other. It shows some of the complexities of real life applications that require the power of an event pattern language. The original version of this example in [GL92] consisted of three architectures in VHDL for a simple 16 bit microprocessor at three commonly used design levels of abstraction: instruction level, register transfer level (RTL) and gate level. This work reported the results of using mappings written in VAL (VHDL annotation language) to control ....

....are generalized in Rapide to event pattern connection rules. This feature allows dynamic architectures. Finally, event patterns are used in Rapide to define mappings between architectures, thus allowing for hierarchical and comparative simulation, as described in our earlier work on VAL [GL92] At present a simulation toolset for Rapide 1.0 is being tested on industrial examples of software and hardware architectures of moderate complexity. The simulator produces posets. Analysis tools display simulator output graphically, automatically check output for violations of formal ....

Benoit A. Gennart and David C. Luckham. Validating discrete event simulations using event pattern mappings. In Proceedings of the 29th Design Automation Conference (DAC), pages 414--419, Anaheim, CA, June 1992. IEEE Computer Society Press.

....We omit discussion of time intervals and other Rapide timing constructs. Interval timing constructs are similar to those used in timing specification in [AGH 88, ALG 90] 3. 3 Pattern Language The concept of event patterns is similar to that developed in [LHM 86, Ros91, Gen91, GL92] Event patterns define subsets of poset computations. Patterns may be constructed using the following syntax: pattern : basic pattern j pattern binary pattern operator pattern j pattern ( iterator operator binary pattern operator ) j pattern where guard j ( placeholder list ....

Benoit A. Gennart and David C. Luckham. Validating discrete event simulations using event pattern mappings. In Proceedings of the 29th Design Automation Conference (DAC), pages 414--419, Anaheim, CA, June 1992. IEEE Computer Society Press.

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B. A. Gennart and D. C. Luckham. Validating discrete event simulations using event pattern mappings. In DAC '92: Proceedings of the 29th ACM/IEEE conference on Design automation, pages 414--419, Los Alamitos, CA, USA, 1992. IEEE Computer Society Press.

No context found.

A. Benoit and D. Luckham. Validating Discrete Event Simulations Using Event Pattern Mappings. In ACM/IEEE Design Automation Conference, pages 414-- 419, 1992.

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