K. Y. Yun, B. Lin, D. Dill, and S. Devadas, "Performance-driven synthesis of asynchronous controllers," in Proc. Int. Conf. Computer-Aided Design, 1994, pp. 550--557.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....part of asynchronous design is controller design, because of complex hazard avoidance requirements and its implications on performance of overall circuits. This paper focuses on the performance side of controller design, namely an efficient synthesis technique for extended burst mode circuits [19, 17, 20], which have proved to be practically useful and promised good performance. The new synthesis algorithm described in this paper is geared toward synthesizing high performance circuits for small to medium size extended burst mode specifications. Previous synthesis techniques for (extended) ....

....this paper is geared toward synthesizing high performance circuits for small to medium size extended burst mode specifications. Previous synthesis techniques for (extended) burstmode specifications targeted two level AND OR circuits [19, 13] or multi level circuits reduced from multiplexor trees [20]. These implementations are derived from on set covers of next state logic. These synthesis techniques produced efficient, high performance circuits for large specifications, utilizing a global logic minimization algorithm [14] However, while attempting to synthesize circuits for specifications ....

K. Y. Yun, B. Lin, D. L. Dill, and S. Devadas. Performancedriven synthesis of asynchronous controllers. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 550--557, November 1994.

....AND OR; b) e in generalized C element. B. 3D Machine Operation There are three types of machine cycles in a 3D state machine: Type I. an input burst followed by a concurrent output and state burst; 3 Many alternative implementations for burst mode circuits have been proposed elsewhere [37], 38] Type II. an input burst followed by an output burst followed by a state burst; Type III. an input burst followed by a state burst followed by an output burst. The selection of a machine cycle depends on the required level of concurrency and the next state logic synthesis method used. ....

K. Y. Yun, B. Lin, D. L. Dill, and S. Devadas, "Performance-driven synthesis of asynchronous controllers," in Proc. International Conf. ComputerAided Design (ICCAD), Nov. 1994, pp. 550--557.

....sending of another byte, while the second, to state 6 represents the signaling of the end of transmission. Using this design style, SCSI interfaces, cache controllers, an infrared communications controller, as well as a variety of interface specifications have been designed with promising results [9, 12, 17, 16, 18, 7]. This paper provides efficient algorithms for quantifying the energy consumption of burst mode circuits implemented with twolevel or multi level logic. Since different modes of circuit operation mayconsume different amounts of energy, we must determine the relative likelihood of executing ....

....AND CIRCUIT IMPLEMENTATIONS In this paper we restrict ourselves to specifications that are extended burst mode diagrams and hazard free multi level logic implementations, as defined in this section. 3. 1 Extended Burst Mode Specifications An extended burst mode asynchronous finite state machine [18] is specified by a state diagram which consists of a finite number of states, a set of labeled state transitions connecting pairs of states, and a start state. These specifications extend the original burst mode format introduced in [11] Figure 1 shows an example of the extendedburst mode ....

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K. Y. Yun, B. Lin, D. L. Dill, and S. Devadas. Performance-driven synthesis of asynchronous controllers. In IEEE 1994ICCAD Digest of Papers. IEEE Computer Society Press, 1994.

....47 45 79 60 15 15 25 21 4 24 dramc 51 40 64 46 20 17 23 20 22 28 5380fsm 217 181 459 345 59 54 114 100 17 25 cache ctrl 720 494 886 532 215 161 245 172 31 40 Table 4.2: Comparisons to locally clocked machine. 4.5. 3 Experimental Results Using BDD Synthesis We used the 3D synthesis tool [78] in conjunction with the combinational synthesis tool [35] to perform experiments (see table 4.3) on many examples previously synthesized by the method described in [75] With very modest efforts to find the optimal variable order, 3 most of the examples required less area than the two level ....

K. Y. Yun, B. Lin, D. L. Dill, and S. Devadas. Performance-driven synthesis of asynchronous controllers. In Proceedings of the 1994 IEEE/ACM International Conference on Computer Aided Design. IEEE Computer Society Press, November 1994.

....part of asynchronous design is controller design, because of complex hazard avoidance requirements and its implications on performance of overall circuits. This paper focuses on the performance side of controller design, namely an efficient synthesis technique for extended burst mode circuits [19, 17, 20], which have proved to be practically useful and promised good performance. The new synthesis algorithm described in this paper is geared toward synthesizing high performance circuits for small to medium size extended burst mode specifications. Previous synthesis techniques for (extended) ....

....this paper is geared toward synthesizing high performance circuits for small to medium size extended burst mode specifications. Previous synthesis techniques for (extended) burstmode specifications targeted two level AND OR circuits [19, 13] or multi level circuits reduced from multiplexor trees [20]. These implementations are derived from on set covers of next state logic. These synthesis techniques produced efficient, high performance circuits for large specifications, utilizing a global logic minimization algorithm [14] However, while attempting to synthesize circuits for specifications ....

K. Y. Yun, B. Lin, D. L. Dill, and S. Devadas. Performancedriven synthesis of asynchronous controllers. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 550--557, November 1994.

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K. Y. Yun, B. Lin, D. Dill, and S. Devadas, "Performance-driven synthesis of asynchronous controllers," in Proc. Int. Conf. Computer-Aided Design, 1994, pp. 550--557.

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