N. Kushiyama et al., "A 500-Megabyte/s Data Rate 4.5 M DRAM," IEEE J. Solid-State Circuits, Vol. 28, No. 4, Apr. 1993, pp. 490-498. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
High Speed Electrical Signalling: Overview and Limitations - Horowitz, Yang, Sidiropoulos (1998) (3 citations) (Correct)
....bandwidth between systems and IC s must scale accordingly. Currently, communication links used in a variety of applications are all approaching Gbit sec data rates. The applications of these links are diverse: computer to peripheral connections [1] local area networks [2] memory busses [3], and multiprocessor interconnection networks [4] 5] There is concern that these links will soon run into the fundamental limits of electrical signalling. To examine this concern, we look at the limitations of CMOS implementations of high speed links and show that the performance of the CMOS ....
....the performance, a high gainbandwidth product amplifier is desirable. An effective design is a regenerative amplifier, whose gain is exponentially related to the bandwidth due to the positive feedback. The most common form of this de multiplexing is employed in low latency parallel systems [3], 10] Two receivers are used on each input, one of them triggered by the positive and one by the negative edge of the clock as illustrated in Figure 8 (a) Each receiver has 1 2 cycle to sample (while resetting the amplifier) while another 1 2 cycle (one full bit time) can be allocated for the ....
[Article contains additional citation context not shown here]
Kushiyama, N. et al. "A 500-megabyte/s data rate 4.5 M DRAM" IEEE Journal of SolidState Circuits, April 1993. vol.28, no.4, p. 490-8
A Microarchitectural Performance Evaluation of a 3.2 Gbyte/s.. - Tim Stanley (Correct)
....medium bandwidth, signal rise fall times, signal setup hold times, clock skew, and transmission delay. The ideal bus would be limited by the bandwidth of the interconnect medium, and failing this by the signal rise fall times. We have adopted a signaling scheme similar to that used by Rambus 1 [11] that is limited by the signal rise fall times rather than by clock skew or signal setup hold time. It is suitable for board level and multi chip module packaging, and matches the clock bandwidth with the data bandwidth. Figure 3 shows a typical BIU transaction. Each chip generates its own ....
N. Kushiyama, et al., "A 500-megabyte/s data-rate 4.5m DRAM," IEEE Journal of Solid-State Circuits, vol. 28, no. 4, pp. 490--498, April 1993.
a 0.8μm CMOS 2.5Gbps Oversampling Receiver and Transmitter .. - Yang, Horowitz (Correct)
....depends on the current pulled by one of the series stack. Because the swing is designed to be 600 800mV the stack behaves as a current source even with the gate pulled to VDD. The output current can be controlled through programming the number of current source legs activated by the pre driver [6]. To simplify the current design for testing, the programmability is not implemented. Instead, the pre driver s supply is adjustable to control the output swing. Since the pseudo differential output does not guarantee constant current, switching noise still exists. To keep the switching noise and ....
N. Kushiyama, et al., "A 500-Megabytes/s Data-Rate 4.5M DRAM", IEEE J. of Solid State Circuits, vol. 28, no. 4, pp. 490-498, Apr 1993. YANG and HOROWITZ: A 0.8µm CMOS 2.5Gbps Oversampling Receiver and Transmitter. . . 14 FIGURE CAPTIONS
High-Speed Electrical Signaling: Overview and Limitations - Horowitz, Yang, Sidiropoulos (1998) (13 citations) (Correct)
No context found.
N. Kushiyama et al., "A 500-Megabyte/s Data Rate 4.5 M DRAM," IEEE J. Solid-State Circuits, Vol. 28, No. 4, Apr. 1993, pp. 490-498.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC