John G. Maneatis and Mark A. Horowitz, "Precise Delay Generation Using Coupled Oscillators" IEEE J. .Solid-State Circuits, vol. 28,NO.12 DEC 1993  Home/Search   Document Details and Download   Summary   Related Articles   Check

....the resulting output frequency of the VCO with respect to the # bit (# ##in this implementation) control word is neither linear nor monotonic. The available set of discrete frequencies are sufficient for our needs and intended by design. In our implementation, a wide frequency range ICO is used [7]. This was chosen because of some nice tunability and sensitivity behaviors of the ICO. Shown in Fig. 6 are the details of the circuit. As described in [7] the diode tied MOSFET in parallel with the current source provides a nice symmetrical load for the differential pair devices in the delay ....

....set of discrete frequencies are sufficient for our needs and intended by design. In our implementation, a wide frequency range ICO is used [7] This was chosen because of some nice tunability and sensitivity behaviors of the ICO. Shown in Fig. 6 are the details of the circuit. As described in [7], the diode tied MOSFET in parallel with the current source provides a nice symmetrical load for the differential pair devices in the delay cells. This symmetric load maintains a relatively steady signal swing that has reduced sensitivity to process and temperature variations and a wide range of ....

J. Maneatis and M. Horowitz, "Precise delay generation using coupled oscillators," Dig. ISSCC, pp. 118-119, Dec. 1993.

....additional tester circuitry onto a single die. This enables the construction of testers with large numbers of I O channels while at the same time, maintaining short signal paths between the tester and DUT. The DGR integrated sixteen I O channels and a 256 cycle vector memory onto a single chip [23]. It was intended only for functional test and therefore could only to drive and sample the DUT on clock cycle boundaries. Nevertheless, this part demonstrated the feasibility of building a complete single chip, CMOS functional tester. The Testarossa improved on the DGR by adding pin electronics ....

....edge within 1 16 of a FO 4 delay [31] and measure the timing of clock edges to an arbitrary precision [17] it appears possible to constrain phase errors to within about 3 of a FO 4 delay. This is significantly better than previously reported data for multi phase clock generators. Maneatis in [23] reports DNL phase spacing errors of 14.3 of a FO 4 delay in a 2m process and Yang reports similar DNL measurements in [37] for uncompensated clock generators. Potentially even more important however, is the robustness of the technique as unexpectedly large static phase offsets are a reoccurring ....

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J. Maneatis et. al. "Precise Delay Generation Using Coupled Oscillators," IEEE Journal of Solid State Circuits, vol. 28, no. 12, pp. 1273-1282, Dec. 1993.

.... The basic structure of this DLL resembles standard DLL designs, but supply controlled inverters as delay elements require the delay line control signal supply the current required by the inverters [42] Other delay elements such as current starved inverters [22] and differential delay buffers [27] [31] found in conventional designs have high impedance control nodes and can be directly controlled by the loop filter output. So, PD DN UP Figure 4.4. Delay locked loop block diagram this design requires a buffer to isolate the control voltage to the inverters from the loop filter output. ....

....between the two loops on the order of 10x is desirable. Given the good noise rejecting properties of this regulating amplifier, a low jitter delay line consisting of supply controlled inverters can be obtained. Its operation is in some ways similar to replica biased differential delay elements [31]. While replica biasing in the differential buffers dynamically adjusts its current to compensate for power supply fluctuations, the regulating amplifier rejects power supply noise to the control voltage itself. Filtering the control voltage through the regulating amplifier also provides good ....

J.G. Maneatis, "Precise delay generation using coupled oscillators," Ph.D. dissertation, Stanford University, Stanford, CA, June 1994.

....Figure 4.1: PLL block diagram . 74 Figure 4.2: Voltage controlled ring oscillator schematic. 75 Figure 4. 3: Delay element and its biasing scheme using a half buffer replica [64] shown in (a) and the load element I V characteristics in (b) 76 Figure 4.4: Low swing to high swing converter . 78 Figure 4.5: Power spectral density of phase noise of an oscillator with different tracking bandwidths. ....

....error. The finite bandwidth of the loop limits this tracking. The magnitude of the resulting jitter depends on the amount of supply noise and whether the supply noise can be tracked or rejected. Designers of PLLs have demonstrated peak to peak jitter of less than 1 FO 4 delay ( 104] 56] and [64]) even in noisy environments. Consequently, the effective timing margin can be as large as 2 1. The jitter accumulates in an oscillator. A common variation for systems where clock and data are the same frequency is to use a voltage controlled delay line (VCDL) instead of a VCO [47] to avoid the ....

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J.G. Maneatis, et al., "Precise delay generation using coupled oscillators," IEEE Journal of Solid-State Circuits, Dec. 1993, vol.28, no.12, p. 1273-82 179

....dithering of the control voltage around the locking point fixed and independent of the operating frequency. The delay line is implemented as a series of eight delay elements. In order to improve noise sensitivity, the DLL uses differential delay elements with symmetric controlledimpedance loads [51]. Figure 4.20 shows the delay element schematic diagram. The control voltage V CP is a buffered version of the charge pump control voltage, while V CN is generated by a replica feedback biasing circuit which keeps the delay through the elements constant and independent of supply variations. In ....

....at delay line buffer outputs, they can result in a loss of the receiving clock. Thus, the first duty cycle adjuster is used at the input of the delay line. This DCA uses two differential delay elements connected in a feedback loop with NMOS capacitors that remove the AC component of the voltages [51]. The output of the input DCA is tied to the output of the first delay element, compensating for both duty cycle variations and common mode offsets of the input clock. The second DCA is embedded in the final stage which converts the low swing clock output of the delay line to a full swing CMOS ....

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J. Maneatis and M. Horowitz, "Precise delay generation using coupled oscillators," IEEE Journal of Solid-State Circuits, vol. 28, no. 12, pp. 1273-1282, Dec 1993.

....in Figure 12. The quality of phase spacing generated by a ring oscillator and interpolators is measured to have errors of less than 8 of the ideal phase spacing. Alternative techniques for finely spaced phase generation, such as coupled oscillators and delay verniers, are described in [27], 29] 30] Regardless of whether the clock generation employs a PLL or a DLL, a high loop tracking Because the interpolators are not perfect linear interpolators because they are not perfect integrators [7] Figure 12: Delay element and interpolator design V bias V ctrl V c ck ip ck in ....

....as a percentage of bit widths can be expected to increase with decreasing transistor feature sizes. However, the static nature of these errors will enable their cancellation by using static timing calibration schemes. For example, the interpolating clock generation architectures described in [7] [27] can be augmented with digitally controlled phase interpolators [31] and digital control logic to effectively cancel device induced phase errors. In addition to random device mismatches, decreasing bit times in low latency parallel interfaces, will magnify the effect of mismatches on the ....

Maneatis, J.G. et al. "Precise delay generation using coupled oscillators" IEEE Journal of Solid-State Circuits, Dec. 1993. vol.28, no.12, p. 1273-82

....Reset TResetH Phase Detector CountEnabH UpdateRRH Clk Boundary Scan Interface Clock Gen Main Loop d d DC Bias DC Bias Figure 3.1. Block diagram of ClkAlign, showing major components. All of the circuitry in the Clock Decimation Loop uses Mark Horowitz s version of the replica bias technique [MANE93]. The phase detector of the Decimation Loop drives a charge pump which generates the analog control voltage for the delay line and other components; the replica bias generator is also included in this block. The Main Loop is a digital control system in which a phase detector (latch) samples ....

....with no overshoot, and to provide delay that is insensitive to power supply variations. The latter objective is the most difficult to realize. To this end, we use differential delay stages, with their excellent common mode noise rejection, and the replica bias technique described in [YOUN92] and [MANE93]. In our implementation, the differential stages use a simple nmos current source, and pmos loads constructed as shown in Figure 3.2. VCtrl I V I V V=VCtrl 2 V=VCtrl 1 Figure 3.2 PMOS loads used in delay line. If the two pfets, drawn the same size, are connected as shown in the figure, then as the ....

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J. Maneatis and Horowitz, M., "Precise Delay Generation Using Coupled Oscillators," JSSC 28-12, pp. 1273-1282.

....52 element sampled delay line. Half a delay element of resolution is lost performing this simplistic division, but since half delay elements are not available in the TDL2 delay line this cannot be avoided. Some potential techniques for producing fractional delay element delays are described in [22] and [23] and may be useful for future work. Figure 47. Simplified block diagram for the propagation delay measuring circuit. The outputs of the sample register are then applied to a leading one detector that identifies the transition bit in the register and outputs a signal with that bit set ....

J. Maneatis and M. Horowitz, "Precise Delay Generation Using Coupled Oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273-1282, Dec. 1993.

....in [16] differential symmetry is insufficient, and the symmetry of each half circuit is important. One practical method to achieve this symmetry is to use more linear loads, such as resistors or linearized MOS devices. This method reduces the 1 noise upconversion and substrate and supply coupling [20]. Another revealing implication, shown in Appendix A, is the reduction of the 1 corner frequency as increases. Hence for a process with large 1 noise, a larger number of stages may be helpful. One question that frequently arises in the design of ring oscillators is the optimum number of stages ....

J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273--1282, Dec. 1993.

....load, reduction of the upconversion might be achieved through the use of a perfectly linear resistive load, because the rising and falling behavior is governed by an RC time constant and makes the individual waveforms more symmetrical. It was first observed in the context of supply noise rejection [15], 16] that using more linear loads can reduce the effect of supply noise on timing jitter. Our treatment shows that it also improves low frequency noise upconversion into phase noise. Another symmetry related property is duty cycle. Since the ISF is waveform dependent, the duty cycle of a ....

J. G. Maneatis, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273--1282, Dec. 1993.

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J. Maneatis and M. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273--1282, Dec. 1993.

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J. Maneatis and M. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1273--1282, Dec. 1993.

....made of inverters cannot provide both true and complementary clock outputs because a CMOS inverter is a single ended buffer. Two single ended ring oscillators can be coupled to generate true and complementary clocks. The theory of coupling multiple oscillators in general is described in [46]. Each buffer stage of the ring oscillator is basically a delay interpolator that has two inputs; one input from the previous stage in the same ring and the second input coupled from the other ring. The delay interpolator consists of two inverters with their outputs shorted together. There are ....

J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273--1282, Dec. 1993.

....frequency. The data source to each I O transmitter can either be a pseudorandom bit sequence (PRBS) or an externally loaded data pattern. The core DLL generates six differential clocks at 30 phase spacings [23] 24] that are distributed to all the I Os using lowswing differential buffers [25], 26] In the default operation mode, a clean system clock (cleanClk) is used for clock generation 2 . As mentioned earlier, on start up, the chip undergoes a calibration phase during which the transmitter sends a clock stream along each data line. The data pins are calibrated sequentially ....

J. Maneatis and M. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273--1282, Dec.

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J. Maneatis, and M. Horowitz, "Precise Delay Generation Using Coupled Oscillators," IEEE J. of Solid State Circuits, vol. 28, no. 12, pp. 1273-1282, Dec 1993. YANG and HOROWITZ: A 0.8m CMOS 2.5Gbps Oversampling Receiver . . . . .9 FIGURE CAPTIONS

....in this work still require a significant amount of power and area compared to other components of the transceiver. This is especially true for the interpolation circuits (with multi phase generation) A more power and area efficient scheme, such as the one based on the idea of coupled oscillators [33], might be better suited for highly integrated applications. 110 ChaptS 8: Conclusion 109 [1] M. J. E. Lee, W. J. D lly, and P. Chiang, A 90 mW 4 Gb s equalized I O circuit with input offset cancellation, in ISSCC Dig. Tech. Papers, pp. 252 253, Feb 2000. 2] M. J. E. Lee, W. J.Dq ly, and ....

J. G. Maneatis and M. A. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-StBw Circuit vol. 28, pp.

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J. Maneatis and M. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273--1282, Dec. 1993.

....the number of samples the minimum required three samples would increase the power dissipated on the sampling clock and the area occupied by the input samplers by a factor of three. Additionally, positioning the sampling edges precisely with low intra edge jitter is a difficult problem by itself [9]. The solution we chose to implement is the analog equivalent of majority voting. The receiver integrates current on a capacitor based on the polarity of the input voltage and determines the polarity of the incoming data at the end of the sampling period. This method requires only a single ....

....control voltage around the locking point fixed and independent of the operating frequency. The delay line is implemented as a series of eight currentstarved delay elements. In order to improve the supply sensitivity of the DLL, we used differential delay elements with symmetric impedance loads [9]. Fig. 14 shows the delay element schematic diagram. The control voltage is a buffered version of the charge pump control voltage, while is generated by a replica feedback biasing circuit which ensures that the delay through the elements stays constant independent of variations on supply and ....

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J. Maneatis and M. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, no. 12, Dec. 1993.

....by individual clock phases. Furthermore, clock data recovery is achieved by a 3 oversampling of each data bit. Thus, the receiver requires a total of 24 clock phases to support both the oversampling and the 1 : 8 demultiplexing. Various techniques exist for generating multiple clock phases [2] [3]. The receive side uses a sixstage ring oscillator ( PLL) followed by phase interpolators to generate intermediate phases (ick[23 : 0] between the ring oscillator edges (ck[11 : 0] 1] Similar to the PLL, eight different clock phases tapped from a four stage ring oscillator ( PLL) control the ....

....select the correct sample to track the phase change. This indicates a maximum phase tracking rate of 83 ps 3 ns. The criterion of tracking both and PLLs accumulation is met because the VCO elements supply noise sensitivity is (percent of frequency change per percent of supply noise [1] [3]) 5 corresponding to 30 ps 3 ns for a 10 supply step, which is less than the tracking rate. If the phase change is slower than 83 ps 3 ns, the 3 byte accumulation offers some robustness by averaging any uncertainty in the transition detection due to high frequency bit to bit noise. A smaller ....

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J. Maneatis and M. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273--1282, Dec. 1993.

....(PD) output selects phases and controls the phase interpolation. B. Core Loop To minimize the jitter supply sensitivity, all the delay buffers in the design, from the input clock (in CLK) to the output of the phase interpolator ( use differential elements with replica feedback biasing [6]. In order to linearize the loop gain and obtain large operating range, the core loop charge pump current is scaled along with the VCDL buffer current as illustrated in Fig. 6 [7] Voltage is generated through the replica feedback biasing circuit while is a buffered version of the charge pump ....

J. Maneatis and M. Horowitz, "Precise delay generation using coupled oscillators," IEEE J. Solid-State Circuits, vol. 28, pp. 1273--1282, Dec. 1993.

....(PD) output selects phases f, y and controls the phase interpolation. B. Core Loop To minimize the jitter supply sensitivity all the delay buffers in the design, from the input clock (in CLK) to the output of the phase interpolator (Q) use differential elements with replica feedback biasing [6]. In order to linearize the loop gain and obtain large operating range, the core loop charge pump current is scaled along with the VCDL buffer current as illustrated in Figure 6 [7] Voltage V cn is generated through the replica feedback biasing circuit while V cp is a buffered version of the ....

J. Maneatis and M. Horowitz, "Precise Delay Generation Using Coupled Oscillators," IEEE Journal of Solid State Circuits, vol. 28, no. 12, Dec. 1993.

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John G. Maneatis and Mark A. Horowitz, "Precise Delay Generation Using Coupled Oscillators" IEEE J. .Solid-State Circuits, vol. 28,NO.12 DEC 1993

No context found.

Maneatis, J., M. Horowitz, "Precise Delay Generation Using Coupled Oscillators," IEEE Journal of Solid-State Circuits, vol 28, no 12, Dec. 1993, pp. 1273-82

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J. Maneatis, "Precise Delay Generation Using Coupled Oscillators," Ph.D. Dissertation,

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J.G. Maneatis et al., "Precise Delay Generation Using Coupled Oscillators," IEEE J. Solid-State Circuits, Vol. 28, No.12, Dec. 1993, pp. 1,273-1,282.

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