AHMAD,I .AND CHEN, C. Y. R. 1991. Post-processor for data path synthesis using multiport memories. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '91, Santa Clara, CA, Nov. 11-14). IEEE Computer Society Press, Los Alamitos, CA, 276--279.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....connected to every bus as required by the allocation results in STAR. Balakrishnan et al. 18] proposed an approach of grouping registers to form a multiport memory module. They also proposed an approach to minimize the interconnection between ports on a multiport memory and functional units. MAP [19] enhanced Balakrishnan s idea, while using same ILP approach. Kim and Liu [20] changed the overall procedure of datapath allocation for multiport memories. They first determine the interconnections between memory ports and functional units, and then group the variables to form memory modules. They ....

Ahmad, I. and Chen, C. Y. Roger, "Post-Processor For Data Path Synthesis Using Multiport Memories," Proc. ICCAD 91, pp.276-279, 1991.

....far are substantiated in Section 6, followed by conclusions and our future directions of research in Section 7. 2 Background memory allocation and M D signal assignment To our knowledge, almost all techniques tackling the storage allocation problem employ a scheduling driven scalar oriented view [26, 13, 2, 10, 1, 22, 24] where the control steps of production and consumption are assumed to be known for each individual scalar signal. This strategy is mainly due to the fact that applications targeted in conventional highlevel synthesis contain a relatively small number of signals (at most of the order of 10 3 of ....

.... experimented examples leading to port polytopes of up to hundreds of points and the computational effort remained even then of the order of minutes (see Section 6) 5 Signal to memory assignment Several binary ILP formulations were proposed in the past to solve the signal to memory assignment [1, 2, 22]. These assignment models employ as binary variables x ij which defines the assignment of the scalar signal i to memory j. If several memories are present, the maximum number of signals that can be assigned is limited to a few hundreds, due to limits of commercial ILP packages (as LAMPS, ....

I.Ahmad, C.Y.R.Chen, "Post-processor for data path synthesis using multiport memories," Proc. IEEE Int. Conf. Comp. Aided Design, Santa Clara CA, pp.276-279, Nov. 1991.

....algorithm by Kurdahi [1] and the edge coloring algorithm by Stok [2] Once the register bits are created, they are clustered together to create a logical memory. Examples of memory bit clustering algorithms are MIMOLA [3] the clique partitioning algorithm in [4] and 0 1 ILP formulation in [5]. A set of algorithms such as MESA [6] and algorithms proposed by IMEC [7] and Philips [8] perform generic memory creation from register bits. Furthermore, a logical memory may also be created by using component instantiation in high level hardware description languages. The created logical ....

I. Ahmed and C. Chen. Post processor for data path synthesis using multiport memories. In IEEE Trans. Computer-Aided Design, 1991.

.... outcome of the background memory estimation or memory mapping tools (e.g. for memory allocation, memory assignment, address generation) Note that this high level memory management stage is fully complementary to the traditional high level synthesis step known as register allocation assignment [24, 13, 2, 11, 1, 22] which deals with individual storage places for scalars in registers or register files, after scheduling. Manual transforming the specification during the early system level to explore the cost measures for several alternatives is tedious and error prone. To remove this design time bottle neck, in ....

....ports. Again, this results in an updated flowgraph specification. A prototype tool HIMALAIA has been developed [3] 5. In place mapping (see also figure 4) investigation of experimental methods for deciding on in place storage of multi dimensional signals. A[1024] B[1023] 16bits 12bits A[0] A[1]=fix 16,4 (1) B[1] fix 12,4 (2) i: 2. 1023) begin A[i] f(A[i 1] B[i 1] B[i] g(A[i 2] B[i 1] end; A[1024] B[1023] 16bits 12bits Figure 3: Illustration of two memory allocation alternatives for a simple DFL specification where it is assumed that 2 cycles are available to execute the ....

[Article contains additional citation context not shown here]

I. Ahmad and C.Y.R. Chen. Post-processor for data path synthesis using multiport memories. In Proc. Int. Conf. on Comp.-Aided Design, pages 276--279, Nov. 1991.

....1995. See IEEE copyright procedure 1995. high level storage organization for the multi dimensional signals in our CATHEDRAL script [36] Note that this high level memory management stage is fully complementary to the traditional high level synthesis step known as register allocation assignment [31, 19, 15, 1, 29] which deals with individual storage places for scalars, after scheduling. Part of this effort is also needed in the CATHEDRAL context, but this decision on scalar memory management is postponed to our low level data path mapping stage [15] Three main partly conflicting objectives can be ....

....them is vital to producing high quality designs in a reasonable time. 2 Background memory size estimation: context and state of the art To our knowledge, almost all techniques for dealing with the allocation of storage units are scalar oriented and employ a scheduling directed view (see e.g. [1, 2, 19, 29, 31]) where the control steps of production consumption for each individual signal are determined beforehand. This applies also for memory register estimation techniques (see e.g. 18, 13] and their references) This strategy is mainly due to the fact that applications targeted in conventional ....

[Article contains additional citation context not shown here]

I. Ahmad, C.Y.R. Chen, "Post-processor for data path synthesis using multiport memories," in Proc. Int. Conf. on Comp.-Aided Design, Nov. 1991, pp. 276-279.

....stage includes a decision on: the number and type of (background) memory units, the signal to memory binding , and the detailed internal organisation of the memory units. Note that this is fully complementary to the traditional high level synthesis step known as register allocation assignment [5, 1, 4] which deals with individual storage places for scalars, after scheduling. Part of this effort is also needed in the CATHEDRAL context, but this decision on scalar memory management is postponed to our low level data path mapping stage [4] Three main partly conflicting objectives can be ....

....on more accurate costs. This paper contributes to the memory allocation issue from step (1) 2 Background memory allocation and quantitative data flow analysis To our knowledge, almost all techniques for dealing with the allocation of storage units employ a scheduling directed view (see e.g. [5, 1] and their references) where the control steps of production consumption for each individual signal are determined beforehand. This strategy is mainly due to the fact that applications targeted in conventional highlevel synthesis contained few loops and even less MD signals. The CDFGs addressed ....

I.Ahmad, C.Y.R.Chen, "Post-processor for data path synthesis using multiport memories," Proc. IEEE Int. Conf. Comp. Aided Design, Santa Clara CA, pp.276279, Nov. 1991.

....TODOS performs the variable to storage binding for user defined variables quite early. Example: Assuming that reg has been declared as an instance of ThreeportRAM and that reg is the designated memory for variables, TODOS would transform the variables of our running example into: reg[0] reg[1] 2 reg[2] 1; a = reg[0] b = reg[1] reg[2] 0; i = reg[2] 5 Scheduling The idea underlying scheduling in TODOS is that an even distribution of operations over control steps like the one generated by force directed scheduling (Paulin (1987) is not a primary design goal. The ....

....for user defined variables quite early. Example: Assuming that reg has been declared as an instance of ThreeportRAM and that reg is the designated memory for variables, TODOS would transform the variables of our running example into: reg[0] reg[1] 2 reg[2] 1; a = reg[0] b = reg[1]; reg[2] 0; i = reg[2] 5 Scheduling The idea underlying scheduling in TODOS is that an even distribution of operations over control steps like the one generated by force directed scheduling (Paulin (1987) is not a primary design goal. The primary goal is to create the fastest possible ....

I. Ahmad and C.Y. Chen. Post-processor for data path synthesis using multiport memories. Int. Conf. on Computer-Aided Design (ICCAD), pages 276--9, 1991.

....Faculty Research Grant. y A preliminary version of this paper appeared in the 1994 Design Automation Conference. for i = 1 to N for j = 2 to N a[i] a[i] 1 2 (b[i] j Gamma 1] b[i] j Gamma 2] b[i] j] F (b[i] j] end end before optimization for i = 1 to N t1 : a[i] t2 : b[i][1]; t3 : b[i] 0] for j = 2 to N t1 : t1 1 2 (t2 t3) b[i] j] F (b[i] j] t2 : t3; t3 : b[i] j] end a[i] t1 end after optimization Figure 1: Removing redundant memory traffic. a memory system) since a primary store (e.g. register storage) sufficiently large enough would be ....

....arise in doing so: 1) the exact grouping of variables so as to minimize the number of modules used; and, 2) the interconnections now necessary to connect modules to functional units. Balakrisnan et al. 3] provide a solution which places primary importance on variable grouping. Ahmad and Chen [1] extend Balakrishnan s approach to take into account the commutative property of operations, thus allowing the connection of a memory module to either input of a functional unit. Kim and Liu [20] note that the first issue heavily influences the second, and, thus, in their approach, they place ....

I. Ahmad and C. Y. R. Chen. Post-processor for Datapath Synthesis Using Multiport Memories. Proceedings of the ACM/IEEE International Conference on Computer-Aided Design, pages 276--279, November 1991. San Jose, California.

....figure 2, there is only one remaining parameter to fix in each of the address equations, namely the base address or offset of the array in memory. However, especially for the dynamic approaches, making a good choice for these offsets is not trivial. In the scalar context, binary) ILP formulations [18, 19], iterative) line packing [20, 21] graph coloring [22] or clique partitioning [23] techniques have provided satisfactory results for register( file) allocation and signal to register assignment. Unfortunately, these techniques are not feasible when the number of scalars becomes too large, which ....

I. Ahmad and C.Y.R. Chen. Post-processor for data path synthesis using multiport memories. In Proc. IEEE Int. Conf. Comp. Aided Design, pages 276--279, Santa Clara CA, Nov. 1991.

No context found.

AHMAD,I .AND CHEN, C. Y. R. 1991. Post-processor for data path synthesis using multiport memories. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '91, Santa Clara, CA, Nov. 11-14). IEEE Computer Society Press, Los Alamitos, CA, 276--279.

No context found.

AHMED,I.AND CHEN, C. Y. R. 1991. Post-processor for datapath synthesis using multiport memories. In Proceedings of the ACM/IEEE International Conference on CAD. (San Jose, CA, Nov.) 276--279.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC