D. E. Duarte, N. Vijaykrishnan, and M. J. Irwin, "A clock power model to evaluate impact of architectural and technology optimizations." IEEE Tran. VLSI, vol. 10, no. 6, Dec. 2002, pp. 844-855. Home/Search Document Details and Download
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D. E. Duarte, N. Vijaykrishnan, and M. J. Irwin, "A clock power model to evaluate impact of architectural and technology optimizations." IEEE Tran. VLSI, vol. 10, no. 6, Dec. 2002, pp. 844-855.
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