J. Hoogerbrugge and H. Corporaal. Transport-triggering vs. operationtriggering. In 5th International Conference on Compiler Construction, April 1994. 29  Home/Search   Document Not in Database   Summary   Related Articles   Check

....itself is not fixed, but synthesis is driven by a user defined structural description. ASIC synthesis is done with a commercial tool, while software synthesis, both for general purpose and specialized processors, is done with an existing retargetable compiler developed by Hoogerbrugge 44 et al. HC94] Ben Ismail et al. IAJ94] and Voss et al. VIJK94] start from a system specification described in SDL ( SSR89] The specification is then translated into the Solar internal representation, based on a hierarchical interconnection of communicating processes. Processes can be merged and split, ....

J. Hoogerbrugge and H. Corporaal. Transport-triggering vs. operation-triggering. In 5th International Conference on Compiler Construction, April 1994.

....of interest. Topics References Specification, Verification ASAR [6] A.Benveniste, G. Berry [9] Codes [12] Cosmos [42] 49] Simulation Insulin [105] Ptolemy [13] 53] J.A. Rowson [93] B. Kerridge [56] Code Generation Capsys [5] Chess [58] CodeSyn [64] C. Monahan, F. Brewster [70] MOVE [36]; Oscar [57] PEAS 1 [2] Analysis ADAM [48] X. Hu [37] J. Gong, et al. 29] Partitioning Cosyma [21] 34] A. Kalavade , E.A. Lee [54] K.A. Olukotun, et al. 78] Tosca [3] Vulcan [32] 31] Case Studies GPS [102] 101] Graphics Processor [67] JPEG [30] Powertrain [37] Priority Queue ....

....and due to the compilationefficiency which is required for these high performance applications, i.e. a high quality code must be produced for complex processors. First approaches in this direction include FlexWare s CodeSyn [64] Cathedral s Chess [58] or the compiler of the MOVE system [17] [36]. 4 A special problem for video processing are the high simulation times [1] This can be avoided in part by a structured top down approach which reduces the number of simulations at a low level, and in addition, fast instruction set simulators like Insulin [105] or the simulator of the MOVE ....

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J. Hoogerbrugge and H. Corporaal. Transport-triggering vs. operation-triggering. In Proc. ACM Int. Conf. Compiler Construction, Edinburgh, 1994.

....output of the unit. The latency is a variable in the architecture template. Registers. The size and the number of read write ports in the register file can be specified. Currently, only a single general purpose register file can be used. This restriction is due to the MOVE scheduler [ 34] 82] [ 81] which is used in the compiler back end. In the future this restriction might be removed so that several small register files can replace the large register file. This would be more efficient in the synthesis of the processor hardware. Number and type of ports. The datapath has different types of ....

....system. This means, design time is focused on improving the critical parts of existing programs rather than re inventing them for a slightly different processor architecture. DESIGN METHODOLOGY 39 Translation of the program into a sequential assembler code. The GNU MOVE compiler [ 82] [ 81], developed by J. Hoggerbrugge at Delft Technical University, is used in this thesis. The compiler is based on the GNU gcc g with a special back end to generate MOVE assembler code. For the purpose of this thesis the MOVE code can be considered as a generic 3operand RISC code with no special ....

J. Hoogerbrugge and H. Corporaal. Transport-triggering vs. operationtriggering. In Proc. ACM Int. Conf. Compiler Construction, Edinburgh, 1994.

....do not program a processor by specifying operations, which cause implicit data transports between GPRFs and FUs, but we specify the data transports directly. In a recent paper we have shown that transport triggered architectures (TTAs) need less busses and do not need associative bypass circuitry [HC94] In this paper we will show that TTAs need significantly less GPRF ports than traditional operation triggered architectures (OTAs) as well. We shall describe why TTA need less GPRF ports and report experiments that quantify the reduction. So far we have only been talking about VLIWs and not ....

Jan Hoogerbrugge and Henk Corporaal. Transport-Triggering vs. OperationTriggering. In International Conference on Compiler Construction, Edinburgh, Scotland, April 1994.

....paths, a scheduler should have a larger scope than a single basic block at a time. A basic block is a sequence of consecutive statements in which the flow of control enters at the beginning and leaves always at the end. Several scheduling scopes can be found which go beyond the basic block level [1]. The most general scope currently used is called a region [2] This is a set of basic blocks that corresponds to the body of a natural loop. Since loops can be nested, regions can also be nested in each other. Like natural loops, regions have a single entry point (the loop header) and may have ....

....currently used is called a region [2] This is a set of basic blocks that corresponds to the body of a natural loop. Since loops can be nested, regions can also be nested in each other. Like natural loops, regions have a single entry point (the loop header) and may have multiple exits [2] In [1] a speedup over 40 is reported when extending the scheduling scope to a region, the problem of region scheduling is that it requires loops in the control flow graph with a single entry point. These flow graphs are called reducible flow graphs. Fortunately, most control flow graphs are reducible, ....

[Article contains additional citation context not shown here]

Jan Hoogerbrugge and Henk Corporaal. Transport-triggering vs. operation-triggering. In Lecture Notes in Computer Science 786, Compiler Construction, pages 435--449. Springer-Verlag, 1994.

....paths, a scheduler should have a larger scope than a single basic block at a time. A basic block is a sequence of consecutive statements in which the flow of control enters at the beginning and leaves always at the end. Several scheduling scopes can be found which go beyond the basic block level [1]. The most general scope currently used is called a region [2] This is a set of basic blocks that corresponds to the body of a natural loop. Since loops can be nested, regions can also be nested in each other. Like natural loops, regions have a single entry point (the loop header) and may have ....

....currently used is called a region [2] This is a set of basic blocks that corresponds to the body of a natural loop. Since loops can be nested, regions can also be nested in each other. Like natural loops, regions have a single entry point (the loop header) and may have multiple exits [2] In [1] a speedup over 40 is reported using region scheduling. The problem of region scheduling is that it requires loops in the control flow graph with a single entry point. These flow graphs are called reducible flow graphs. Fortunately most control flow graphs are reducible, nevertheless the problem ....

[Article contains additional citation context not shown here]

Jan Hoogerbrugge and Henk Corporaal. Transport-triggering vs. operation-triggering. In Lecture Notes in Computer Science 786, Compiler Construction, pages 435--449. SpringerVerlag, 1994.

....do not program a processor by specifying operations, which cause implicit data transports between RFs and FUs, but we specify the data transports directly. In a recent paper we have shown that transport triggered architectures (TTAs) need fewer busses and do not need associative bypass circuitry [HC94] In this paper we will show that TTAs need significantly fewer RF ports than traditional operation triggered architectures (OTAs) as well. We shall describe why TTA need fewer RF ports and report experiments that quantify the reduction. So far we have only been talking about VLIWs and not about ....

Jan Hoogerbrugge and Henk Corporaal. Transport Triggering vs. Operation Triggering. In Proceedings of the International Conference on Compiler Construction, Edinburgh, Scotland, April 1994.

....It is shown that a operation based architectures require up to 30 more transport capacity, however in order to efficiently exploit this capacity by a TTA we need a scheduling scope far beyond basic block boundaries. The latter is currently under development. First results will be publiced in [13]. It is shown that scheduling beyond basic blocks gives a 40 performance improvement. For a more extensive description and evaluation of the MOVE concept see e.g. 10, 14, 11, 15] 4 MOVE framework The ultimate goal of the MOVE project is to establish a framework for the semi automatic ....

Jan Hoogerbrugge and Henk Corporaal. Transport-triggering vs. operation-triggering. In Compiler Construction conference CC-94, 1994.

....some time (depending on the latency of the adder) the result can be moved to r3. At a first glance it looks like a typical RISC operation requires three move operations. However, a number of optimizations are possible which reduce the number of move operations to an average of about two (see e.g. [3]) This means that less transport capacity is needed. In practice most FUs implement multiple operations (like having a single FU for both add and subtract) These operations are distinguished by mapping multiple trigger identifiers on the same physical trigger register. Conditional execution is ....

....to generate instruction level parallel code, while exploiting all the available hardware resources. To this purpose it uses profiling data (like execution frequencies) from the simulator. The scheduler uses extended basic block scheduling and speculative execution in order to enhance code motions [3]. 4 Experiments We divide the problem of finding a good application specific TTP into two subtasks, resource optimization and connectivity optimization. Resource optimization consists of finding the right match of resources, such as which FUs to use, how many buses, how many GPRs, and how many ....

Jan Hoogerbrugge and Henk Corporaal. Transport-triggering vs. operation-triggering. In Lecture Notes in Computer Science 786, Compiler Construction, pages 435--449. Springer-Verlag, 1994.

.... An architecture that exploits instruction level parallelism (ILP) should be able to read and write multiple register values concurrently; ILP architectures therefore require multi ported register files (RFs) One approach to exploit ILP is to use a transport triggered architecture (TTA) see [1, 2]. Although TTAs reduce the register port requirements with more than 50 as compared to a VLIW with a shared RF [3] the number of required ports can still be substantial for large TTA configurations. However, a large monolithic multi ported RF increases chip area, causes extra delay and power ....

Jan Hoogerbrugge and Henk Corporaal. Transporttriggering vs. operation-triggering. In Lecture Notes in Computer Science 786, Compiler Construction, pages 435--449. Springer-Verlag, 1994.

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J. Hoogerbrugge and H. Corporaal. Transport-triggering vs. operationtriggering. In 5th International Conference on Compiler Construction, April 1994. 29

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