K. R. Lakshmikumar, R. A.Hadaway, M. A. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design", IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057-1066, 1986  Home/Search   Document Not in Database   Summary   Related Articles   Check

....doesn t hold for integrated circuits. Many other approaches to yield maximization assume that C = const. Unfortunately, this assumption doesn t hold anymore when local variations and mismatch are to be considered. Since # V th 1 WL, the covariance matrix C depends on the design parameters d [1, 16]. With local variations, Y can be improved not only by enlarging A, but also by reducing the variance of s. Depending on the initial design, both factors are necessary to increase the yield. Therefore, a modern yield optimization technique must account for both. Optimization of eq. 5) in ....

K. Lakshmikumar, R. Hadaway, M. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design", IEEE J. SC, 1986.

....are best, and devices should be built up of unit elements. When this cannot be done, ratios of perimeter to area should be matched for all elements. In many cases the space surrounding matched elements is filled with identical dummy elements to eliminate edge of the array effects. McCR81, SHYU84, LAKS86, PELG89, NAKA91, BAST91] Early DAC implementations in bipolar and hybrid technologies depended upon precision, thin film resistors to implement matched devices, and these are still found in many products today. These resistors are typically configured in an R 2R ladder, which creates binary ....

....is usually insignificant, but in this case, with matched devices separated by distances up to 1000 m, both effects are significant. 6.3.4. 1 Random mismatch Several studies of random mismatch behavior have been done, looking at causes and models for capacitor and MOS device mismatches [SHYU84,LAKS86,PELG89] The two earlier studies emphasized edge effects causing variations in device width or length, and formulated models based on these assumed causes of device mismatch. Data was then fit to these models. Unfortunately, the test data used did not have a wide enough range of device aspect ....

K.R. Lakshmikumar, R. A. Hadawy, and M.A. Copeland, "Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design," IEEE Journal of Solid State Circuits, SC-21(6), Dec. 1986, pp. 1057-66. [Creates a model for mismatch and fits limited data to that model, for a 3 m technology. Derivation of contributions of mismatch to DAC INL.]

....the circuit. This is equal to the ratio of the individual gains of the integrator (K int ) and the ramp (K ramp ) K = K int K ramp (3. 1) Because ratios of capacitors and currents in analogue VLSI can be accurately matched, as opposed to their absolute values which suffer from a big variation [105, 106,107] the control over the gain is improved. It is these integrators that we have implemented by the use of analogue VLSI in our Palmo cells. 3.3 Signal Representation After having considered the implementation of a typical Palmo cell the signalling mechanism needs to be defined in order to design ....

....in equation (3. 5) can be modified by switching between the elements of a capacitor array, and the ratio of the currents can be electrically modified, with sufficient accuracy [108,106,109,69] it is realised that the scale factor K is fully programmable and insensitive to absolute values [110,105,111][8, Appendix C] 3.4.2 Charge Injection A C F C F F C C F V c V in V in V in V c V c B F F F Figure 3 8: MOS switch implementations with reduced clock feedthrough. Charge injection is a very well known phenomenon in which some part of the charge stored in the channel of a MOS ....

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K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterization and modeling of mismatch in MOS-transistors for precision analog design," IEEE Journal of Solid-State Circuits, vol. 21, no. 6, pp. 1057--1066, 1986. Bibliography 143

....is between 1 and 3.5 dB better than S2I orig. Compared to S2I simple, the improvement is in the range of 4 dB. SI match achieves the lowest distortion values, although these measured results are worse than expected (see [4] due to a transistor mismatch which is larger than the values reported in [16], 17] Note, however, that with regard to power and area efficiency, the multiphase circuit introduced here is more than three times better than the one based on matching. Of course, in a differential structure, part of the circuit SI match can be shared (for example, the offset term in [4] need ....

K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design," IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057--1066, Dec. 1986.

....are shown, one for each of the 8 non faulty measured chips. For simulation purposes, it is very convenient to have a dependence for the mismatch standard deviations as functions of transistors width W and length L. Many such dependencies have been proposed in the specialized literature [1] 2] [8]. In the present study we just intend to obtain a mathematical function able to fit the measured data. We do not intend to provide a physical interpretation to the resulting fitting coefficients. Consequently, we selected a very general mathematical function and let the fitting routines select the ....

K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterization and Modeling of Mismatch in MOS Transitors for Precision Analog Design," IEEE Journal of Solid-State Circuits, vol. SC-21, No. 6, pp. 1057-1066, December 1986.

....of the electrical parameters of the manufactured devices. These deviations from theory or simulated results are often critical for the desired functionality of the chip. Additionally, the impact of the process parameter deviations increases with the down scaling of the standard CMOS processes used [1, 7]. As an example the minimum possible standard deviation of the ooeset voltage of a transconductance ampli er ( g. 1) is depicted in gure 2. The results were acquired by performing a multi dimensional optimisation of the transistor dimensions (width and length for each MOST) The computations are ....

Kadaba R. Lakshmikumar, Robert A. Hadaway, and Miles A. Copeland. Characterization and modeling of mismatch in MOS transistors for precision analog design. IEEE Journal of Solid-State Circuits, SC21 (6):10571066, December 1986.

....of the previous work is found in Section 2. In Section 3 we present our approach of extracting and modeling mismatch, along with the results obtained. Section 4 presents our conclusions. 2 Previous Work In most of the previous work, either the systematic mismatch is not considered at all [3] [4] or its effect is modeled as a stochastic process with a long correlation distance [1] 5] In the Fourier domain this effect is modeled as a fixed low frequency contribution with a spatial frequency inversely proportional to the wafer diameter. Normal distribution is considered a reasonable ....

....4r oe V T (VGS Gamma VT ) oe K K (2) Here, oe I , oe V T , and oe K are the standard deviations of I , VT and K , respectively. I , K , and VT are the expected values of random variables I , K , and VT , respectively, and r is the coefficient of correlation between VT and K . In [4] a model is proposed for oe K and oe V T by considering different causes of mismatch. The variance in VT is modeled by considering the variations in different charge quantities and the gate oxide capacitance per unit area. Edge effects, variations in channel mobility, and gate oxide capacitanceper ....

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K. R. Lakshmikumar, R. A. Hadaway and M. A. Copeland, "Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design", IEEE J. of Solid-State Circuits, Vol. SC-21, No. 6, pp. 1057-1066, Dec. 1986.

....s1 s1 s1 s1 s1 s1 s1 s1 0.015 0.01 0.005 0 0.005 0.01 Mismatches (dx x) Components Figure 8: Measured INL and Component Mismatches Component mismatches, in general, are caused by underlying basic statistical process variations. In this design, assumed were underlying process variations [11] [12] such as the flat band voltage variations, aVFB , and the standard deviation of the MOS transistor widths and lengths. Using the component mismatch data measured at two reference currents and using a basic mismatch formula [13] the process mismatches can estimated. Table 3 shows the results. The ....

K. R. Lakshmikumar, R. A. Hadaway and M. A. Copeland, "Characterization and modeling of Mismatch in MOS Transistors for Precision Analog Design," IEEE Journal of Solid State Circuits, vol. SC-21, n. 6, pp. 1057--1066, December 1986.

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K. R. Lakshmikumar, R. A.Hadaway, M. A. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design", IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057-1066, 1986

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K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design," IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057--1066, 1986.

No context found.

Lakshmikumar, K. R., Hadaway, R. A., and Copeland, M. A. Characterization and modeling of mismatch in mos transistors for precision analog design. IEEE Jouranl of Solid-State Circuits 21 (Dec. 1986), 1057--1066.

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K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterization and modeling of mismatch in MOS transitors for precision analog design." IEEE Journal of Solid-State Circuits SC-21(6), pp. 10571066, 1986.

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K. R. Lakshmikumar et al, "Characterization and Modeling of Mismatch in MOS transistors for Precision Analog Design", IEEE JSSC, Vol. sc-21, No. 6, pp. 1057-1066, Dec. 1986.

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