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J. H. Anderson, F. N. Najm, and T. Tuan, "Active leakage power optimization for FPGAs," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Monterey, CA, Feb. 2004, pp. 33--41.

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This paper is cited in the following contexts:
A Dual-VDD Low Power FPGA Architecture - Gayasen Lee Vijaykrishnan (2004)   (1 citation)  Self-citation (Tuan)   (Correct)

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J. H. Anderson, F. Najm, and T. Tuan. "Active Leakage Power Optimization for FPGAs". 2004.


Power Modeling and Characteristics of Field - Programmable Gate Arrays   (Correct)

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J. H. Anderson, F. N. Najm, and T. Tuan, "Active leakage power optimization for FPGAs," in Proc. ACM Int. Symp. Field-Programmable Gate Arrays, Monterey, CA, Feb. 2004, pp. 33--41.


FLAW: FPGA Lifetime AWareness - Suresh Srinivasan Prasanth (2006)   (Correct)

No context found.

J. H. Anderson, F. Najm, and T. Tuan. "Active leakage power optimization for FPGAs," In Proceedings of ACM/SIGDA International Symposium on Field-programmable gate arrays, 2004.


HARP: Hard-wired Routing Pattern FPGAs - Satish Sivaswamy Gang   (Correct)

No context found.

J. H. Anderson, F. Najm, and T. Tuan. "Active Leakage Power Optimization for FPGAs". In Proc. of ACM/SIGDA International Symposium on Field programmable gate arrays, 2004.

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