A. Balboni, W. Fornaciari, and D. Sciuto, "Cosynthesis and cosimulation of control-dominated embedded systems," Design Automat. Embedded Syst., vol. 1, no. 3, pp. 257--289, July 1996.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... First, process versions require a variable granularity size of the elements used during the high level transformation and synthesis steps to better utilize the architecture components (AC) In previous approaches, the size of these function elements ranges from processes in the input language [1] down to functions [12] and basic blocks or elementary threads [5, 6, 8] in ASIP design even down to individual statements [13] The optimization potential for a system scheduling and allocation process (for brevity, we will call it mapping process) rises with finer granularity (small elements) ....

A. Balboni, W. Fornaciari, and D. Sciuto, "Cosynthesis and Co--Simulation of Control--Dominated Embedded Systems", in Design Automation for Embedded Systems, Vol. 1, Nr. 3, 1996.

....versions of the input description. An important parameter in hardware software co synthesis is the granularity in partitioning, allocation, and scheduling, i.e. the size of the elements used in co synthesis. The size of these function elements ranges from processes in the input language [1] down to functions [11] and basic blocks or elementary threads [5, 6, 8] in ASIP design even down to individual statements [12] The size of these function elements defines the granularity. The optimization potential for system level scheduling and allocation rises with finer granularity (small ....

A. Balboni, W. Fornaciari, and D. Sciuto, "Cosynthesis and Co-Simulation of Control-Dominated Embedded Systems", in Design Automation for Embedded Systems, Vol. 1, Nr. 3, 1996.

....of scheduling and allocation proliferates which will have a negative impact on the run time of scheduling and allocation and it may limit the system size or it may require the use of simpler heuristics. In previous approaches, the size of these segments ranges from processes in the input language [1] down to functions [16] and basic blocks or elementary threads [7, 9, 11] in ASIP design even down to individual statements [17] Work which is related to the work presented here can be found in the HW SW codesign domain. However, those approaches do not consider overlapping functionality. The ....

A. Balboni, W. Fornaciari, and D. Sciuto, "Cosynthesis and Co--Simulation of Control--Dominated Embedded Systems", in Design Automation for Embedded Systems, Vol. 1, Nr. 3, 1996.

....1 Introduction Despite many improvements in co synthesis during the past years, the range of applications and target architectures is still rather limited and prevents design space exploration for more complex architectures. There is work in reactive, control dominated systems, such as [3, 6, 7, 8] and work in data dominated or computation oriented systems, such as [1, 9, 10, 11] which differ in the type of time constraints and data operations which they can handle as well as in the optimization process. Many applications, such as mobile communications, however, show a mixture of both ....

....The scheduling algorithm can be selected by the user, e.g. Rate Monotonic and Deadline Monotonic. Hardware synthesis creates one hardware module per CFSM with point to point communication between hardware modules while hardware modules and processor communicate via shared registers. TOSCA [3] assumes a target architecture similar to the one in POLIS, however, user interaction, the partitioning algorithm, and the input languages are different. Again, there is one hardware module per FSM and point to point communication between FSMs while hardware software communication uses driver ....

A. Balboni, W. Fornaciari, D. Sciuto, Cosynthesis and Co-- Simulation of Control--Dominated Embedded Systems, Design Automation for Embedded Systems, Vol. 1, No. 3, Kluwer, 1996.

....high level specification. 4 Simulation Simulation lets designers execute a design model of their system [19] The model can range from the initial targetindependent description to the output of intermediate synthesis stages. Many hardware software design automation tools have simulation support [1, 18, 22], however IPCHI5 NOOK supports a novel technique called selective focus simulation [12] This approach simulates at the highest level of abstraction whenever possible to achieve the fastest simulation speed. Since designers may sometimes need to inspect low level details in isolated regions of the ....

BALBONI,A.,FORNACIARI,W.,AND SCIUTO, D. Co-synthesis and cosimulation of control-dominated embedded systems. Design Autmation for Embedded Systems (July 1996).

....over these channels are done with remote procedure call initiated form a master, the master can either be a send or a receive function. The difference between these two approaches is that in CoWare have a well defined strategy for refinement of the channels. The two codesign systems TOSCA [18] and Vulcan [19] have also similar communication strategy, both are using static channels and send receive service functions to access the channel. The difference is that TOSCA handle only buffered and unbuffered send receive functions while Vulcan also support blocking send receive. 9 In Polis ....

....4. 3 Mapping algorithms The COSMOS group is the only research group so f ar, that have developed mapping algorithms to allocate and bind architectural elements to implement the logical communication channels [15] Other groups use direct mapping of the service functions on some implementation [1,11,14,18,19] or manual refinement [8,5] instated of some heuristic. On lower level transformation several groups have reported algorithms [3,5,9,12] to translate low level protocols. Chinook system they present algorithms for generating the control signals on a micro controller to interface components. This ....

[Article contains additional citation context not shown here]

A. Balboni, W. Fornaciari, D. Sciuto, Co-synthesis and Co-simulation of Control-Dominated Embedded Systems, Design Automation for Embedded Systems, 1(3), pp. 257-289, 1996. 12

....MATLAB SIMULINK. A similar development can be observed for event oriented models of computation, which are of special importance for reactive systems, e.g. STATEMATE in automotive engineering or SDL in the area of telecommunications. There are many other examples, mainly from academia, like OCCAM [2], ESTEREL [1] and LOTOS [4] each of which represents a different model of computation. In hardware software codesign, programming languages like VHDL, C, C or Java are usually used as a basis for the description of more abstract models. The commercial codesign system CoWare uses a client server ....

A. Balboni, W. Fornaciari, and D. Sciuto. Cosynthesis and cosimulation of control-dominated embedded systems. Journal on Design Automation of Embedded Systems, 1(3):257--288, June 1996.

....many improvements in co synthesis during the past years, the range of application and the target architectures of the individual approaches are still very limited and prevent design space exploration for more complex architectures. There is work in reactive, control dominated systems, such as [1, 2, 3, 4] which covers single microcontrollercoprocessor architectures typically shared memory or pointto point interconnect and work in data dominated or computation oriented systems, such as [5, 6] which use single processor coprocessorarchitectures or relatively simple communication structures, such as ....

....t pi;min = t pv;min t cyc , where t cyc is the FSM cycle time, t pi is the process instantiation time, and t pv is the process instantiation interval. This model is the basis for most co synthesis approaches in the control domain, where hardware processes are mapped to individual FSMs [1, 4, 3]. If there are more complex operations on data, which take several clock cycles, operation scheduling is needed and the FSM transition time increases while instantiation is still spontaneous as long as the FSM is not busy in transition. This leads to an increasing process instantiation interval: ....

A. Balboni, W. Fornaciari, D. Sciuto, Cosynthesis and CoSimulation of Control-Dominated Embedded Systems, Design Automation for Embedded Systems, Vol. 1, No. 3, Kluwer, 1996.

....over these channels are done with remote procedure calls initiated from a master, the master can either be a send or a receive function. The difference between these two approaches is that CoWare has a well defined strategy for refinement of the channels. The two codesign systems TOSCA [2] and Vulcan [11] have also similar communication strategy, both are using static channels and send receive service functions to access the channel. The difference is that TOSCA handles only buffered and unbuffered non blocking send receive functions while Vulcan also supports blocking ....

....dual FIFO. Mapping algorithms The COSMOS group is the only research group so far, that has developed mapping algorithms to allocate and bind architectural elements to implement the logical communication channels [7] Other groups use direct mapping of the service functions on some implementation [2,4,8,11,13] or manual refinement [19,20] instated of some heuristic. For lower level transformations several groups have reported algorithms [5,16,17,19] to translate low level protocols. The Chinook system includes algorithms for generating the control signals on a micro controller to interface components. ....

[Article contains additional citation context not shown here]

A. Balboni, W. Fornaciari, D. Sciuto, Co-synthesis and Co-simulation of Control-Dominated Embedded Systems, Design Automation for Embedded Systems, 1(3), pp. 257289, 1996.

....new modularization of the system specification semantically equivalent to the original one. When an acceptable partitioning is found, synthesis of the HW and SW parts can be performed. The SW synthesis passes through an intermediate uncommitted format, called virtual instruction set (VIS) [8], allowing the designer to consider the timing performance when different CPU cores are employed and to make possible a flexible simulation of the cooperating HW and SW based on the same VHDL simulator engine. HW bound modules and interfaces are automatically converted into suitable VHDL ....

A. Balboni, W. Fornaciari, and D. Sciuto, "Co-synthesis and cosimulation of control dominated embedded systems," in International Journal Design Automation for Embedded Systems, vol. 1, no. 3, July 1996.

No context found.

A. Balboni, W. Fornaciari, and D. Sciuto, "Cosynthesis and cosimulation of control-dominated embedded systems," Design Automat. Embedded Syst., vol. 1, no. 3, pp. 257--289, July 1996.

No context found.

A. Balboni, W. Fornaciari, and D. Sciuto, "Cosynthesis and Cosimulation of Control-Dominated Embedded Systems, " J. Design Automation Embedded Systems, Vol. 1, No. 3, Jun. 1996, pp. 257-288.

No context found.

A. Balboni, W. Fornaciari, and D. Sciuto. Co-synthesis and co-simulation of control dominated embedded systems. Journal of Design Automation for Embedded Systems, 1(3):257--289, July 1996.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC