A.A. Jerraya, and K. O'Brien, SOLAR: An Intermediate Format for System-Level Modelling and Synthesis, in "Computer Aided Software/Hardware Engineering," J. Rozenblit, K. Buchenrieder (eds), IEEE Press, Piscataway, N.J., pp 147-175, 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....nodes. Each data node represents either an arithmetic relational logical operation or a read write to a memory or a port. Variations and extensions of CDFG s have been used by many researchers. SOLAR is intended as an intermediate design representation for control dominated mixed HW SW systems [78, 79]. It is based on hierarchical, concurrently executing finite state machines, allowing for the specification of hierarchical communicating FSMs. Tree structures allow for modular specifications. The program state machine (PSM) model integrates a hierarchical, concurrent FSM with programming ....

Ahmed A. Jerraya and K. O'Brien, "SOLAR: An Intermediate Format for System- Level Modelling and Synthesis", Codesign: Computer-aided Software/Hardware Engineering, IEEE Press, Jerzy Rozenblit and Klaus Buchenrieder, 7, pp. 145-175, 1995.

....does not fulfil design constraints the process is restarted, otherwise the system is implemented. The output from the system is an interface graph. 2. 5 COSMOS, Grenoble Jerraya et al. present a system with SDL [64] as a front end which is compiled into an intermediate description, SOLAR [45], which is based on a finite state model extended with concepts of hierarchy and parallelism. The design specification is partitioned by an interactive tool box called Partif [44] Partitioning starts with a set of hierarchical and communication processes which are characterized by a cost function ....

A. A. Jerraya, K. O'Brien, "SOLAR: An Intermediate Format for SystemLevel Modelling and Synthesis", in Computer Aided Software/Hardware Engineering, J. Rozenblit, K. Buchenrieder (eds), IEEE Press, 1994.

....Each data node represents either an arithmetic relational logical operation or a read write to a memory or a port. Variations and extensions of CDFG s have been used by many researchers. 2. 3 SOLAR SOLAR is intended as an intermediate design representation for control dominated mixed HW SW systems [7, 8]. It is based on hierarchical, concurrent finite state machines. The principal building block is a StateTable. It allows the specification of hierarchical and communicating FSMs. In addition, three structures have been added to allow modular specifications. The DesignUnit construct is used to ....

Ahmed A. Jerraya and K. O'Brien, "SOLAR: An Intermediate Format for System-Level Modelling and Synthesis", Codesign: Computer-aided Software/Hardware Engineering, IEEE Press, Jerzy Rozenblit and Klaus Buchenrieder, 7, pp. 145-175, 1995.

....in order to translate the hardware parts into ASICs or virtual hardware processors (emulators) The result is an architecture composed of software components, hardware components and communication components. III.2. System model structure As stated above, the unified system model, named SOLAR[12], is designed to accommodate various system specification languages such as SDL, LOTOS, ESTEREL, SA RT or StateCharts. The philosophy is to allow the designer to use one or more of these languages and to translate these descriptions into SOLAR. This model also constitutes the basis of codesign ....

....to define the most suited architecture and to rapidly derive the first system prototype. Tool support for the methodology could integrate tools for system modelling and validation, and tools for codesign and architecture prototyping. A possible support environment, based on the SOLAR environment[12] for codesign and synthesis tasks, is presented in Figure 11. 15 SA0 State Charts Functionnal and behavioral Spec. StateMate SDL Communication Spec. G ode MULTI FORMALISM COMPOSITION AFRICAS Design safety analysis AFRICAS SYSTEM MODELLING VALIDATION HARWARE SOFTWARE CODESIGN PARTIF Hw Sw ....

A.A.Jerraya, K.O'Brien, "SOLAR: An Intermediate Format for System-Level Modelling and Synthesis", in "Computer Aided Software/Hardware Engineering", J.Rosenblit, K.Buchenrieder (eds), IEEE Press 1994.

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A.A. Jerraya, and K. O'Brien, SOLAR: An Intermediate Format for System-Level Modelling and Synthesis, in "Computer Aided Software/Hardware Engineering," J. Rozenblit, K. Buchenrieder (eds), IEEE Press, Piscataway, N.J., pp 147-175, 1994.

....IV. Section V describes an algorithm for communication unit allocation. Finally, we will present the application of the communication synthesis method on an example before concluding the paper. II. COMMUNICATION MODEL In this paper we will use the communication modelling strategy described in [19]. At the system level, a system is RPC RPCall svc1 c1 RPCall svc1 c2 P1 RPCall svc3 c3 c1 c3 c2 Abstract channel P2 RPCall svc1 c2 P3 RPCall svc3 c3 RPCall svc2 c1 P4 RPCall svc2 c2 RPCall svc4 c3 svc1 svc2 Fig. 1. Processes communicating through abstract channels represented ....

A.A. Jerraya, and K. O'Brien, SOLAR: An Intermediate Format for System-Level Modelling and Synthesis, in "Computer Aided Software/Hardware Engineering," J. Rozenblit, K. Buchenrieder (eds), IEEE Press, Piscataway, N.J., pp 147-175, 1994.

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