P. Vanbekbergen, G. Goossens, and H. De Man. Specification and analysis of tim- ing constraints in signal transition graphs. In Proceedings of the European Design Automation Conference, pages 302-306, March 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....and concurrent systems is the determination of minimum and maximum separations between times of occurrence of events. The results of such an analysis can be used for interface timing verification [15, 39, 9, 72, 92, 97] synthesis, op timization and verification of asynchronous circuits [62, 78, 91, 5, 46, 22], performance analysis and scheduling of concurrent and embedded systems [24, 46, 98, 22] optimal clock scheduling in circuits with latches [17] etc. Unfortunately, finding exact bounds on the time separation of events is computationally intractable when component delays are bounded and the ....

....time algorithm for max and linear systems. The results of the individual subproblems are then combined to obtain the time separation bounds of the original system. The number of subproblems generated by this technique is exponential in the number of min constraints. Vanbekbergen et al. [91] analyzed Signal Transition Graphs (STG) with delay intervals associated with the places of the STG, for applications in asynchronous circuit synthesis. In their terminology, linear, max and min constraints are referred to as constraints of types 1, 2 and 3, respectively. For an STG with V ....

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P. Vanbekbergen, G. Goossens, and H. De Man. Specification and analysis of tim- ing constraints in signal transition graphs. In Proceedings of the European Design Automation Conference, pages 302-306, March 1992.

....circuit complexity than its speed independent counterpart. In order to synthesize timed circuits, it is necessary to determine the difference in the possible firing times between two transitions in a circuit specification. Recently, polynomial time algorithms have been developed by Vanbekbergen [1] and Dill [2] to determine this value for acyclic graphs. To apply these algorithms to circuit synthesis, these results must be expanded to handle cyclic specifications. One approach to this problem is to unfold the cyclic graph into an infinite acyclic graph [3] We have derived a sufficient ....

....Algorithm 2.2 to construct a finite acyclic graph and use Algorithm 2.1 to detect when an occurrence of a rule is not on a critical path. Each time Algorithm 2. 1 is called, if we are given that (e, i e) is one of the enabling events of (f, i) we use the polynomial time algorithms described in [1] or [2] to find the minimum time difference between (e, i e) and (1, i) If it is greater than u, where u is the upper bound on the timing constraint of the rule between these events, then the rule between these events cannot be on a critical path. We also propose an alternative algorithm which ....

P. Vanbekbergen, G. Goossens, and H. De Man. "Specification and Analysis of Timing Constraints in Signal Transition Graphs", 1992. Accepted to EDAC.

....and concurrent systems is the determination of minimum and maximum separations between times of occurrence of events. The results of such an analysis can be used for interface timing verification [15, 39, 9, 72, 92, 97] synthesis, optimization and verification of asynchronous circuits [62, 78, 91, 5, 46, 22], performance analysis and scheduling of concurrent and embedded systems [24, 46, 98, 22] optimal clock scheduling in circuits with latches [17] etc. Unfortunately, finding exact bounds on the time separation of events is computationally intractable when component delays are bounded and the ....

....time algorithm for max and linear systems. The results of the individual subproblems are then combined to obtain the time separation bounds of the original system. The number of subproblems generated by this technique is exponential in the number of min constraints. Vanbekbergen et al. [91] analyzed Signal Transition Graphs (STG) with delay intervals associated with the places of the STG, for applications in asynchronous circuit synthesis. In their terminology, linear, max and min constraints are referred to as constraints of types 1, CHAPTER 4. TIME SEPARATION OF EVENTS: ACYCLIC ....

[Article contains additional citation context not shown here]

P. Vanbekbergen, G. Goossens, and H. De Man. Specification and analysis of timing constraints in signal transition graphs. In Proceedings of the European Design Automation Conference, pages 302--306, March 1992.

....such as: How late can event A occur after event B for arbitrary events A and B. Time separation bounds find use in a wide variety of applications, including interface timing verification [1] 2] 3] 4] 5] 6] synthesis, optimization and verification of asynchronous circuits [7] 8] [9], 10] 11] 12] and performance analysis and scheduling of concurrent systems [13] 11] 14] 12] In addition, it also has applications in the synchronous domain, e.g. optimal clock scheduling in circuits with latches [15] The problem of computing time separation bounds is compounded in ....

....we describe a formalism for representing timing constraints between events. We then characterize a class of choice free systems with repeated events, and formalize the time separation of events problem for such systems. A. Timing Constraint Graph Following existing convention [1] 3] 18] 4] [9], we represent timing constraints between events by a directed, labeled graph, G = V; E) called the timing constraint graph. Vertices in V represent events, and edges in E represent timing constraints between events. In the following, we will use the terms vertices and events interchangeably. We ....

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P. Vanbekbergen, G. Goossens, and H. De Man, "Specification and analysis of timing constraints in signal transition graphs," in Proceedings of the European Design Automation Conference, Mar. 1992, pp. 302--306.

....also solve the separation problem in an event graph with only linear constraints. McMillan and Dill [96] gives the first correct time separation algorithm for an event graph with max constraints. This algorithm is partially based on an earlier incorrect algorithm given in Vanbekbergen et al. [115]. McMillan and Dill also prove that the separation problem in an graph with both max and min constraints is NP Complete. They further propose an exponentialtime algorithm for an event graph with both max and linear constraints. Walkup and Borriello [116] and Yen et al. 123] both propose time ....

P. Vanbekbergen, G. Goossens, and H. De Man. Specification and analysis of timing constraints in signal transition graphs. In Proc. European Design Automation Conf., pages 302--6, 1992.

....read request) An event graph (see Section 2.3) is used to capture the events and propagation delays of the system. Shortest path algorithms have been used to solve problems that contain only linear 79 constraints, e.g. Borriello 88b] and [Brzozowski et al. 91] Both [McMillan Dill 92] and [Vanbekbergen et al. 92] provide an overview of the various types of event graphs and timing constraints for which verification algorithms have been developed (both authors present algorithms for handling non linear constraints) Most of the analysis in this area has dealt with acyclic event graphs, and unfortunately ....

.... . For our example, we have E 0 = fa; bg R 0 = ae a [4;10] 1 7 Gamma a; a [1;2] 0 7 Gamma b; b [1;6] 1 7 Gamma a; b [5;20] 1 7 Gamma b oe : 1 [Myers Meng 92] introduced a similarly modified system. The model can also be viewed as an extension of [McMillan Dill 92] and [Vanbekbergen et al. 92] where we consider cyclic max only or type 2 graphs. To remain consistent with the notation of [Burns 91] we introduce G 0 before G, E 0 before E, etc. i.e. primed variables are introduced before unprimed variables. 109 The occurrence index offset is used to specify how much the ....

P. Vanbekbergen, G. Goossens, and H. D. Man. Specification and analysis of timing constraints in signal transition graphs. In European Design Automation Conference, March 1992.

....event may be enabled by multiple rules, it is possible that the difference in time between the enabled event and some enabling events exceed the upper bound of their timing constraints, but not for all enabling events. These timing constraints are the same as max constraints [15] and type 2 arcs [25]. The conflict relation is added to model disjunctive behavior and choice. When two events e and e 0 are in conflict (denoted e#e 0 ) this specifies that either e can occur or e 0 can occur, but not both. Taking the conflict relation into account, if two rules have the same enabled event and ....

P. Vanbekbergen, G. Goossens, and H. de Man, Specification and analysis of timing constraints in signal transition graphs, in Proceedings of the European Design Automation Conference, 1992.

....at least 10ns before the falling transition of AS L can occur. This is reflected by the associated timing annotation in the protocol signal transition graph. These timing constraints must be verified after the synthesis process, using for example the timing verification techniques reported in [2, 14, 19, 8]. protocol rtzRead; protocol rtzWrite; process shift send : in signal start; channel addrh7:0i, datah7:0i: rtzRead; channel addr outh7:0i, data outh7:0i: rtzWrite; f boolean xh7:0i, yh7:0i; start ; addr y k data x; addr out y k data out (xAE2) start Gamma; g Figure 5: A simple shift send ....

P. Vanbekbergen, G. Goossens, and H. De Man. Specification and analysis of timing constraints in signal transition graphs. In European Design Automation Conference, March 1992.

....in the specification from the given timing constraints. More specifically, in timed circuits, the timing information needed is the minimumand maximum difference in time between any two events (i.e. signal transitions) in a circuit specification. Polynomial time algorithms have been developed [15] [16] to determine the difference in time between any two events in an acyclic graph. Circuit specifications, however, are normally cyclic. Therefore, to apply these algorithms to circuit synthesis, these results must be expanded to handle cyclic specifications. Recently, an algorithm has been proposed ....

....rules, it is possible that the difference in time between the enabled event and some enabling events exceeds the upper bound of their timing constraints, but not for all enabling events. These timing constraints are the same as the max constraints described in [15] and the type 2 arcs described in [16]. Finding timing constraints for a specification is not a trivial task. Rules can be categorized into environment rules (i.e. the enabled event is a transition of an input signal) and internal rules (i.e. the enabled event is a transition of a state variable or output signal) Timing constraints ....

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P. Vanbekbergen, G. Goossens, and H. De Man. "Specification and Analysis of Timing Constraints in Signal Transition Graphs". In Proceedings of the European Design Automation Conference, 1992.

....the specification and the constraints (imposed by the user or environment) that must be satisfied for the system to function correctly. Graph algorithms have been effectively applied to determine the satisfiability (the ranges of allowable values for each variable) of these systems of inequalities [7, 13]. In more complex cases, the temporal relationships may involve minimums and maximums which often lead to disjoint solution spaces and disjunctions between the linear constraints (e.g. f[X,Y] X = 30 or Y = 30 or X Y = 70g) 1, 14] Presburger formulas which consist of affine constraints ....

P. Vanbekbergen, G. Goossens, and H. De Man. Specification and analysis of timing constraints in signal transition graphs. In European Design Automation Conference, March 1992.

....only works on convex regions, this must be avoided. One way to eliminate the single behavioral rule restriction and avoid generating non convex regions is to change the timing semantics of the specification so that rules are never allowed to exceed their maximum bounds (i.e. type 1 semantics [18]) In type 1 semantics, the specification is invalid if a rule cannot fire within its timing range. In real circuits, however, rules typically are allowed to exceed their maximum bounds (type 2 semantics[18] Our geometric timing algorithm eliminates the single behavioral rule restriction and ....

....so that rules are never allowed to exceed their maximum bounds (i.e. type 1 semantics [18] In type 1 semantics, the specification is invalid if a rule cannot fire within its timing range. In real circuits, however, rules typically are allowed to exceed their maximum bounds (type 2 semantics[18]) Our geometric timing algorithm eliminates the single behavioral rule restriction and allows timing analysis of specifications in which rules can expire. In the Orbits algorithm, the timing information is only updated when an event fires. The single behavioral rule restriction can be eliminated ....

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P. Vanbekbergen,G. Goossens, and H. de Man. Specification and analysis of timing constraints in signal transition graphs. In Proceedings of the European Design Automation Conference, 1992.

....to a more general class of specifications. Interface logic verification is an especially troublesome area of circuit design because of the interactions of synchronous and asynchronous components that must meet specific timing requirements. Work by McMillan Dill [7] and Vanbekbergen Goossens De Man [9] has directly addressed this issue by considering graphs whose ranges of delays are determined from the logic implementation. The verification problem is then to determine the separation in time of constrained events and ensure that they fall within the specified bounds. Amon Borriello [3] have ....

....they fall within the specified bounds. Amon Borriello [3] have taken a different approach where the delays are manipulated symbolically leading to a set of inequalities that must hold true for any valid implementation. In all these cases, however, the process graph topology is restricted. 7] and [9] can only handle acyclic graphs while [3] only supports a limited form of inter process communication. In the area of data path synthesis there is a large body of work in allocation and scheduling that considers minimizing hardware by multiplexing. To accomplish this, scheduling constraints must ....

[Article contains additional citation context not shown here]

Peter Vanbekbergen, G. Goossens, and Hugo De Man. Specification and analysis of timing constraints in signal transition graphs. In European Design Automation Conference, March 1992.

....polynomial time approximate algorithm for finding the minimumand maximum time separations between all pairs of events in a concurrent system, given bounded propagation delays between events, and the type of timing constraint (min or max) associated with each event. Unlike several previous works [1, 7, 10, 2, 5], our algorithm has a worst case time complexity that is polynomial in the number of events, and can handle both min and max type constraints in the same system. A limitation of our current approach is that it applies only to systems representable by acyclic timing constraint graphs. However, ....

....for the acyclic max only constraint problem. A branch and bound algorithm for systems with both min and max constraints was also proposed in [7] However, this has a worst case exponential time complexity. Vanbekbergen et al. proposed an algorithm for systems with both min and max constraints in [10]. Unfortunately, their algorithm is incorrect. The work of [8] computes loose bounds on the time separation of events in cyclic graphs containing only max type events. Burks and Sakallah formulated the problem as a min max linear program (mmLP) and proposed two exact algorithms in [2] ....

P. Vanbekbergen, G. Goossens, and H. D. Man. Specification and analysis of timing constraints in signal transition graphs. In Proceedings of the European DAC, Mar. 1992.

....the state space can often be kept to a manageable size. Interface logic verification is an especially troublesome area of circuit design because of the interactions of synchronous and asynchronous components that must meet specific timing requirements. Work by McMillan and Dill [31] Vanbekbergen [39] and Walkup [42] has directly addressed this issue by considering specifications whose ranges of delays are determined from the logic implementation. The analysis problem is then to determine the separation in time of constrained events and ensure that they fall within the specified bounds. Amon ....

P. Vanbekbergen, G. Goossens, and H. De Man. Specification and analysis of timing constraints in signal transition graphs. In European Design Automation Conference, March 1992.

....rules, it is possible that the difference in time between the enabled event and some enabling events exceed the upper bound of their timing constraints, but not for all enabling events. These timing constraints are the same as the max constraints described in [46] and the type 2 arcs described in [73]. CHAPTER 2. TIMED SPECIFICATIONS 19 The conflict relation is added to model disjunctive behavior and choice. When two events e and e 0 are in conflict (denoted e#e 0 ) this specifies that either e can occur or e 0 can occur, but not both. Taking the conflict relation into account, if two ....

....that certain events which appear concurrent in the specification are actually ordered. The timing information which is required for this check is the minimum and maximum difference in time between any two events in the cyclic constraint graph. Polynomial time algorithms have been developed [46] [73] to determine the difference in time between any two events in an acyclic graph. Circuit specifications, however, are normally cyclic. Therefore, to apply these algorithms to circuit synthesis, these results must be extended to handle cyclic specifications. Exponential time algorithms have been ....

[Article contains additional citation context not shown here]

P. Vanbekbergen, G. Goossens, and H. de Man. Specification and analysis of timing constraints in signal transition graphs. In Proceedings of the European Design Automation Conference, 1992.

....to which our analysis applies. Other approaches to the problem of finding bounds on the separation in time of two events have either been inexact or based on a more restrictive graph topology. Loose bounds that may not enable all possible optimizations were obtained by [8] Both [7] and [10] can only handle acyclic graphs, and [2] only supports a limited form of synchronization and concurrency. This paper is composed of five sections. We follow this introduction with a formalization of the problem, a review of the foundation provided by the solution for finite acyclic graphs, and ....

....Section 5 summarizes the contributions of this paper. 2 Problem Formalization Consider a simple concurrent system consisting of three processes that synchronize over two channels a and b, and do some internal computation (delay ranges specified in brackets) repeat f Synchronize a; Compute [4, 10]; g repeat f Synchronize a; Compute [1, 2] Synchronize b; Compute [1, 6] g repeat f Synchronize b; Compute [5, 20] g We represent the system as a directed graph, called the process graph, where the vertices represent events (synchronizations) and the edges are annotated with delay ....

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P. Vanbekbergen, G. Goossens, and H. De Man. Specification and analysis of timing constraints in signal transition graphs. In European Design Automation Conference, March 1992.

....running time than previous methods, and shows how to apply the method to synthesis tasks. I Introduction Temporal behavior of interface circuitry is frequently described using event based representations that relate the occurrence times of events with timing constraints and propagation delays [1, 2, 3, 4, 5, 6]. In this paper, we present an efficient solution to a key problem in the verification and synthesis of interface glue logic, namely, the determination of tight bounds on the temporal separations between events. To verify a synthesized circuit, we must be able to check that the circuit s outputs ....

....upper bounds of the constraint. Previous work has used different models for temporal constraints that make more explicit distinctions between the two types of constraints. McMillan and Dill ( 3] use the terms Linear and Max constraints for timing and delay constraints, respectively. Vanbekbergen ([4]) has a more complete yet, not largely useful, taxonomy that labels timing and delay constraints as type 1 and type 2, respectively. We find it more useful to translate both types into inequalities involving the Max operation. We can express both types of constraints as a system of inequalities ....

Peter Vanbekbergen, Gert Goossens, and Hugo De Man. Specification and analysis of timing constraints in signal transition graphs. In Proceedings of the European Design Automation Conference, March 1992.

.... by the ARPA CSTO Microsystems Program under an ONR monitored contract (N00014 91 J 4041) 1 Introduction Temporal behavior of interface circuitry is frequently described using eventbased representations that relate the occurrence times of events with timing constraints and propagation delays [2, 4, 3, 5, 6, 7]. In this paper, we present an efficient solution to a key problem in the verification and synthesis of interface glue logic, namely, the determination of tight bounds on the temporal separations between events. To verify the correct timing behavior of a synthesized circuit, we must be able to ....

....the constraints. Previous work has used different models for temporal constraints that make more explicit distinctions between the two types of constraints. McMillan and Dill ( 3] use the terms Linear and Max constraints for timing constraints and propagation delays, respectively. Vanbekbergen ([5]) has a more complete yet, not largely useful, taxonomy that labels timing constraints and propagation delays as type 1 and type 2, respectively. We find it more useful to translate both types into inequalities involving the Max operation. We can express both types of constraints as a system of ....

Peter Vanbekbergen, Gert Goossens, and Hugo De Man. Specification and analysis of timing constraints in signal transition graphs. In Proceedings of the European Design Automation Conference, March 1992.

....result in uncertainties in component delays in a chip. Consequently, timing analysis techniques for asynchronous systems with uncertain delays are needed. A central problem in the analysis of asynchronous systems is computing bounds on the time separation between events [4] 5] 6] 7] 8] [9], 10] 11] 12] 13] 14] Existing techniques typically focus on controller behavior and intercontroller communication protocols, that involve synchronization or max type timing constraints in addition to linear constraints between event times. Systems with max only or maxand linear ....

....communication protocols, that involve synchronization or max type timing constraints in addition to linear constraints between event times. Systems with max only or maxand linear constraints have been well studied and efficient algorithms exist for computing time separations in these systems [8] [9], 15] 16] 17] 11] 14] However, modern highperformance asynchronous systems (e.g. the system in [3] make implicit timing assumptions in both the datapath and control to facilitate design of high speed circuits. Therefore, it is important to model and analyze both datapath and controller ....

[Article contains additional citation context not shown here]

P. Vanbekbergen, G. Goossens, and H. De Man, "Specification and analysis of timing constraints in signal transition graphs," in Proceedings of the European Design Automation Conference, Mar. 1992, pp. 302--306.

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P. Vanbekbergen, G. Goossens, and H. D. Man. Specification and analysis of timing constraints in signal transition graphs. In Proceedings of the European Design Automation Conference, pages 302--306, March 1992.

No context found.

Peter Vanbekbergen, Gert Goossens, and Hugo De Man. Specification and analysis of timing constraints in signal transition graphs. In Proceedings of the European Design Automation Conference, March 1992.

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