T. D. Burd and R. W. Brodersen. Energy efficient CMOS microprocessor design. In Proc. Hawaii Intl Conf. Syst. Sciences, pages 288--297, 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....can be conserved. Due to the high peak power demands of the processor, a large body of work has focused on reducing processor energy consumption. Weiser et al. 37] first demonstrated the effectiveness of using Dynamic Voltage Scaling (DVS) to reduce power dissipation in processors. Later work [2, 11, 14, 15, 25, 28 31] further explored the effectiveness of DVS techniques in both real time and general purpose systems. There is also a large body of work that focused on reducing power in other system components, including wireless communication [10, 18, 21, 35] disk drives [6, 7, 22, 24] flash [5, 27] cache ....

T. D. Burd and R. W. Brodersen. Energy efficient CMOS microprocessor design. In Trevor N. Mudge and Bruce D. Shriver, editors, Proceedings of the 28th Annual Hawaii International Conference on System Sciences. Volume 1: Architecture, pages 288--297. IEEE Computer Society Press, 1995.

....have been proposed to reduce the energy consumption of such systems, such as shutting down unused components and low energy circuit designs. With CMOS technology, processor s power is dominated by dynamic power dissipation which is determined by processor supply voltage and clock frequency [4, 6]. By reducing processor clock frequency and supply voltage, we can reduce energy consumption at the cost of performance of processors. Processors with the ability of dynamic voltage scaling (DVS) are currently commercially available [11, 10] There is an interesting trade off between the energy ....

....f , where C ef is the effective switch capacitance, V dd is the supply voltage and f is the processor clock frequency. Processor speed, represented by f , is almost linearly related to the supply voltage: f = k Theta (Vdd GammaV t ) Vdd , where k is constant and V t is the threshold voltage [4, 6]. The energy consumed by a specific task i can be given as E i = C ef Theta V dd Theta c i , where i is the number of cycles needed to execute i . When we decrease processor speed, we also reduce the supply voltage. This reduces processor power consumption cubically with f and reduces ....

T. D. Burd and R. W. Brodersen. Energy efficient cmos microprocessor design. In Proc. of The HICSS Conference, pages 288--297, Maui, Hawaii, Jan. 1995.

....f , where C ef is the effective switch capacitance, V dd is the supply voltage and f is the processor clock frequency. Processor speed, represented by f , is almost linearly related to the supply voltage: f = k Theta (Vdd GammaV t ) where k is constant and V t is the threshold voltage [4, 7]. The energy consumed by a specific task T i can be given as E i = C ef Theta V dd Theta C, where C is the number of cycles needed to execute the task. When decreasing processor speed, we also reduce the supply voltage. This reduces processor power consumption cubically and reduces task ....

T. D. Burd and R. W. Brodersen. Energy Efficient CMOS Microprocessor Design. Proc. HICSS Conference, pp. 288-297, Maui, Hawaii, January 1995.

....packaging and cooling technology and decreases reliability, especially for systems that have many processors. To reduce processor power consumption, many hardware techniques have been proposed, such as shutting down unused parts or reducing the power level of non fully utilized functional units [4, 7]. Processors that have multiple supply voltages (i.e. multiple power levels) have become available in recent years [16] making power management at the processor level possible. Using this feature, several software techniques have been proposed to adjust the supply voltage, especially for mobile ....

....V dd is the supply voltage, C ef is the effective switched capacitance and S is the processor clock frequency, that is the processor speed. Processor speed is almost linearly related to the supply voltage: S = k Delta (V dd GammaV t ) where k is constant and V t is the threshold voltage [4, 7]. Thus, P d is almost cubically related to S: P d C ef Delta 2 . Since the time needed for a specific task is: time = C , where C is the number of cycles to execute the task, the energy consumption of the task, E, is E = P d Delta time C Delta C ef Delta 2 . When decreasing ....

T. D. Burd and R. W. Brodersen. Energy efficient cmos microprocessor design. In Proc. of The HICSS Conference, pages 288--297, Maui, Hawaii, Jan. 1995. 29

....because it requires more expensive packaging and cooling technology and decreases reliability [18] especially for multi processor systems. In order to reduce heat dissipation and to increase reliability, many hardware and software techniques have been proposed to lower processor power consumption [1, 2, 4, 5, 7, 8, 10]. Processors running on multiple supply voltages (i.e. multiple power levels) have become available in recent years [15] making power management at the processor level possible. Using this feature, several software techniques have been proposed to adjust the supply voltage, especially in the area ....

....processor clock frequency. Processor speed S, represented by f , is almost linearly related to the supply voltage: f = k (V dd Gamma V t ) V dd , where k is constant and V t is the threshold voltage. The energy consumption for a specific task is, thus, almost proportional to C ef V dd [1, 2]. To decrease processor speed, we can reduce the supply voltage. This reduces processor power consumption cubically and reduces task energy consumption quadratically at the expense of linearly decreasing speed and increasing a task s latency. 2.2 Task Model We assume a frame based real time ....

T. D. Burd and R. W. Brodersen. Energy Efficient CMOS Microprocessor Design. Proc. HICSS Conference, pp. 288-297, Maui, Hawaii, January 1995

....) dissipation per operation and the critical delay (t d ) can be described by the following equations : E = C eff V , P = C eff V f and t d = k Vdd (Vdd VT ) # ; where,# is a technology dependent factor and k is a constant. From the above three equations, the following can be deduced [2, 11, 10] : by reducing only V dd , both energy and power can be saved at the cost of performance (speed time) slowing down CPU by reducing only f will save power but not energy and by scaling frequency and voltage in a coordinated manner, both energy and power can be saved while maintaining ....

....will be operated with resources operating at multiple voltages and clocked with dynamic clock. Several approaches have been investigated towards reducing power energy consumption in both general purpose and special purpose processors. A dynamic voltage scaled microprocessor system is presented in [2], in which the frequency and the voltage levels to be supplied to the processor core, are determined by the help of operating system. A power efficient compiler in [5] determines the voltage level and clock frequency at compilation time for high level code. The authors in [11] describe a system ....

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T. Burd and R. W. Brodersen. Energy efficient cmos microprocessor design. In Proc. of the 28th Hawaii International Conference on System Sciences, pages 288--297, 1995.

....microprocessors to provide much greater computation per unit of energy and longer total battery life, the fundamental tradeoff between performance and battery life remains critically important. Recently, significant research and development efforts have been made on Dynamic Voltage Scaling (DVS) [2, 4, 7, 8, 12, 19, 21, 22, 23, 24, 25, 26, 28, 30]. DVS tries to address the tradeoff between performance and battery life by taking into account two important characteristics of most current computer systems: 1) the peak computing rate needed is much higher than the average throughput that must be sustained; and (2) the processors are based on ....

....vast majority of microprocessors today, has a voltage dependent maximum operating frequency, so when used at a reduced frequency, the processor can operate at a lower supply voltage. Since the energy dissipated per cycle with CMOS circuitry scales quadratically to the supply voltage (E V ) [2], DVS can potentially provide a very large net energy savings through frequency and voltage scaling. In time constrained applications, often found in embedded systems like cellular phones and digital video cameras, DVS presents a serious problem. In these real time embedded systems, one cannot ....

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BURD, T. D., AND BRODERSEN, R. W. Energy efficient CMOS microprocessor design. In Proceedings of the 28th Annual Hawaii International Conference on System Sciences. Volume 1: Architecture (Los Alamitos, CA, USA, Jan. 1995), T. N. Mudge and B. D. Shriver, Eds., IEEE Computer Society Press, pp. 288--297.

....until they have to be accessed again. A complementary approach, called dynamic voltage scaling (DVS) reduces power even when these resources are still active. Dynamic voltage scaling exploits the fact that a major portion of power of CMOS circuitry scales quadratically with the supply voltage [7]. Lowering the voltage can therefore reduce power dissipation. However, lowering the voltage increases circuit delay. As a result, DVS reduces power at the expense of performance. In this paper, we focus on reducing the energy consumption of non interactive applications running on laptops with ....

T. Burd and R. Brodersen. Energy efficient CMOS microprocessor design. In the 28th Hawaii International Conference on System Sciences (HICSS-95), January 1995.

....workload. Recent advances in This research was supported in part by the Electronics and Telecommunications Research Institute under Grant No. 00104 power supply technology make it possible to create processor cores with varying supply voltages according to application s time constraints [1,2]. Current custom and commercial CMOS chips are capable of operating reliably over a range of supply voltages and efficient variable voltage DC suppliers are available [3,4] Dynamic voltage scaling (DVS) allows a processor to dynamically change its speed and voltage at run time, increasing energy ....

T. Burd and R. Brodersen, "Energy Efficient CMOS Microprocessor Design," 28th Hawaii Int'l Conf. on System Science, Vol. 1, pp. 288-297, Jan. 1995.

....technology. So, the terms power and energy can be used interchangeably because the clock frequency is fixed. Moreover, the power is almost proportional to the switching capacitance, due to the fact that over 90 of the total power dissipation is the switching power in welldesigned circuits [15]. We analyze the power consumption without any schedule and with the optimal schedule when running several embedded applications. Figure 10 shows an optimal instruction sequence example for an FIR filter application. When one basic block is optimized, 8.5 of the total power can be reduced with ....

T.D. Burd and R.W. Brodersen, "Energy efficient CMOS microprocessor design," Proceedings 28th HICSS Conference, vol. I, pp. 288-297, Jan., 1995. 152

....some systems have latency critical tasks. One possible solution is to dynamically vary the voltage according to the processor workload. Recent advances in power supply technology make it possible to create processor cores with varying supply voltages according to application s time constraints [1,2]. Current custom and commercial CMOS chips are capable of operating reliably over a range of supply voltages and efficient variable voltage DC suppliers are available [3,4] Dynamic voltage scaling (DVS) allows a processor to dynamically change its speed and voltage at run time, increasing energy ....

T. Burd and R. Brodersen, "Energy Efficient CMOS Microprocessor Design," 28th Hawaii Int'l Conf. on System Science, Vol. 1, pp. 288-297, Jan. 1995.

....ANALYSIS Let us introduce the general formalism to express power dissipation, the TOSCA codesign framework and the target system architecture. A. Power Dissipation in CMOS Circuits Power dissipation in CMOS devices is composed of both a static and a dynamic component. Anyway, the dominant part [7] is the dynamic part, expressed by the switching activity power where is the supply voltage, is the system clock frequency and is the effective switched capacitance (that is the product of the total physical capacitance of each node in the circuit and the switching activity factor of each node ....

....the speed is the most important design constraint, and area constrained systems, if the area is the most important constraint. Several computational modes characterize the timing constrained systems, depending on the system throughput defined as the number of operations performed in a given time [7]. For microprocessor based embedded systems, we can define three main modes of computation: fixed throughput mode, maximum throughput mode, and burst throughput mode, the latter characterized by a fraction of time performing useful computations, during which the maximum throughput is required, ....

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T. D. Burd and R. W. Brodersen, "Energy efficient CMOS microprocessor design," in Proc. 28th Hawaii Int. Conf. System Sci., HI, 1995.

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T. D. Burd and R. W. Brodersen. Energy efficient CMOS microprocessor design. In Proc. Hawaii Intl Conf. Syst. Sciences, pages 288--297, 1995.

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BURD, T. AND BRODERSEN, R. W. 1995. Energy Efficient CMOS Microprocessor Design. In Proceedings of the 28th Hawaii International Conference on System Sciences. 288--297.

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T. Burd and R. W. Brodersen, "Energy efficient cmos microprocessor design," in Proc. of the 28th Hawaii Intl. Conf. on System Sciences, 1995, pp. 288--297.

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BURD, T. D., AND BRODERSEN, R. W. Energy efficient CMOS microprocessor design. In Proceedings of the 28th Annual Hawaii International Conference on System Sciences. Volume 1: Architecture (Los Alamitos, CA, USA, Jan. 1995), T. N. Mudge and B. D. Shriver, Eds., IEEE Computer Society Press, pp. 288--297.

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T. Burd and R. W. Brodersen, "Energy Efficient CMOS Microprocessor Design," in Proceedings of the 28th Hawaii International Conference on System Sciences, 1995, pp. 288-- 297.

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T. Burd and R. Brodersen, "Energy Efficient CMOS Microprocessor Design," Proceedings of the Twenty-Eighth Hawaii International Conference on System Sciences, 1995, pp. 288 --297.

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T. D. Burd, R. W. Brodersen -- "Energy Efficient CMOS Microprocessor Design" - 28th Hawaii International Conference on System Sciences, Jan. 1995

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T.D.Burd and R.Broderson. Energy efficient CMOS microprocessor Design. In Proc. of the 28th Annual Hawaii International Conference on System Sciences, 1995.

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Thomas D. Burd and Robert W. Brodersen. Energy-efficient cmos microprocessor design. In 28th Hawaii International Conference on System Sciences, pages 288--297, January 1995.

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T. D. Burd and R. W. Brodersen. Energy efficient cmos microprocessor design. In Proc. of The HICSS Conference, pages 288--297, Jan. 1995.

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Thomas D. Burd and Robert W. Brodersen. Energy-efficient cmos microprocessor design. In 28th Hawaii International Conference on System Sciences, pages 288--297, January 1995.

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T. Burd and R. Brodersen, "Energy Efficient CMOS Microprocessor Design," Proceedings of the 28th Annual 596 Hawaii International Conference on System Sciences, 1995, pp. 288 --297.

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Burd T.D., Brodersen R.W.: "Energy efficient CMOS microprocessor design", Proceedings 28th. annual HICSS Conference, Jan. 1995, vol. I, pp. 288-297.

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