G. Snider. Performance-constrained pipelining of software loops onto reconfigurable hardware. In Proc. of the 10th ACM Symposium on Field Programmable Gate Arrays, pages 177--186, 2002. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Increasing Hardware Efficiency with Multifunction Loop.. - Fan, Kudlur, Park, Mahlke (2006) (Correct)
No context found.
G. Snider. Performance-constrained pipelining of software loops onto reconfigurable hardware. In Proc. of the 10th ACM Symposium on Field Programmable Gate Arrays, pages 177--186, 2002.
Cycle-time Aware Architecture Synthesis of Custom Hardware.. - Sivaraman, Aditya (2002) (5 citations) (Correct)
No context found.
G. Snider. Performance-Constrained Pipelining of Software Loops onto Reconfigurable Hardware. Tenth ACM International Symposium on Field-Programmable Gate Arrays, Feb. 2002.
Combining Retiming and Recycling to Optimize the.. - Synchronous Circuits Luca (Correct)
No context found.
G. Snider. Performance-constrained pipelining of software loops onto reconfigurable hardware. In Proc. Intl. Conf. Symp. on FPGAs, pages 177--186. ACM, Feb. 2002.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC