Avior, A., T. Calamoneri, S. Even, A. Litman, and A. Rosenberg, "A tight layout of the butterfly network," Proc. ACM Symp. Parallel Algorithms and Architectures, Jun. 1996, pp. 170-175.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....The layout of interconnection networks has important cost and performance implications for single chip multiprocessors and parallel distributed systems based on such components. Thus, there is currently renewed interest in fi nding effi cient VLSI layouts for various interconnection networks [3, 8, 10, 12, 13, 21, 28, 30, 31, 32, 35]. VLSI layout of interconnection networks is usually derived under the Thompson model, where two layers of wires are assumed. However, the assumption of two wiring layers cease to be realistic as more and more layers of wires become available in VLSI chips at reasonable cost. When the numbers of ....

Avior, A., T. Calamoneri, S. Even, A. Litman, and A. Rosenberg, " A tight layout of the butterfl y network," Theory Comput. Sys., vol. 31, no. 4, 1998, pp. 475-488.

.... 2 4log 2 2 N o N 2 log 2 N area [25, 27] 2 The layout area for the ISN improves the corresponding result given in [22] by a factor of 4 o(1) The following theorem gives a layout for the butterfl y network that is optimal within a factor of 1 o(1) from the lower bound given in [2]. Theorem 4.5 An N node butterfl y network can be laid out in N 2 log 2 2 N o N 2 log 2 N area. Proof: If we unfold an HSN(2; log 2 N 2 cube) we obtain a (log 2 N 2) stage ISN that uses log 2 N 2 dimensional butterfl y networks as the basic modules. If we double up ....

....Trans fo rm in g a 4 Theta 4 IS N in to a 4 Theta 4 bu tte rfl y ne tw o rk . b ) A resu lta n t 16 Theta 16 bu tte rfl y ne tw o rk . see Fig. 2) Therefore, the area of the butterfl y is approximately 4 times that of an ISN; that is N 2 log 2 2 N o N 2 log 2 N : 2 In [2] the same upper bound for the area of a butterfl y network has been presented. The proof given in [2] is, however, considerably more complicated than our construction. It is also interesting that butterfl y networks can be laid out based on the layout of a complete graph. Generalized hypercubes, ....

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Avior, A., T. Calamoneri, S. Even, A. Litman, and A. Rosenberg, " A tight layout of the butterfl y network," Proc. ACM Symp. Parallel Algorithms and Architectures, Jun. 1996, pp. 170-175.

....performance achieved by lowering various performance hindrances, such as signal propagation delay, drive power, and fraction of data transfers to off chip destinations. This explains the reintensified research on finding efficient VLSI layouts and packaging, especially for butterfly networks [1, 10, 11, 16, 21, 26, 27]. Efficient layouts and packaging considerations for other interconnection networks can be found in [7, 8, 12, 13, 24] Butterfly networks are among the most important topologies for building commercial and experimental parallel computers, special purpose processors, and network switches. ....

....and packaging considerations for other interconnection networks can be found in [7, 8, 12, 13, 24] Butterfly networks are among the most important topologies for building commercial and experimental parallel computers, special purpose processors, and network switches. Recently, Avior et al. [1] proposed a VLSI layout for butterfly networks under the grid model, showing that an N node butterfly network can be laid out in N 2 log 2 2 N o i N 2 log 2 N j area using two layers of wires. They also showed that the layout area is optimal within a factor of 1 o(1) when area is ....

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Avior, A., T. Calamoneri, S. Even, A. Litman, and A. Rosenberg, "A tight layout of the butterfly network," Theory Comput. Sys., vol. 31, no. 4, 1998, pp. 475-488.

....the cases when the order of the inputs and outputs is fixed or can be arbitrarily permuted, respectively; in both cases, the leading constant is the best possible. The best previously known upper bound for the fixedorder case was the N 2 result that follows from the work of Wise [29] See also [1] for bounds when the inputs and outputs may be anywhere within the grid area. Our first bound provides the standard interface of a stand alone butterfly, while the second bound is useful when the butterfly is used as part of a larger circuit in which we can optimize the wiring. For example, using ....

A. Avior, T. Calamoneri, S. Even, A. Litman, and A. Rosenberg. A tight layout of the butterfly network. In Proc. of the 8th ACM Symposium on Parallel Algorithms and Architectures (SPAA '96), pages 170--182, 1996.

....layout; and the other is to reduce the long wires in the layout while keeping the asymptotically optimal area. This paper reports the result coming from our effort in trying to achieve the first goal. Research in graph embedding and VLSI layout has developed many powerful techniques [2, 5] which can produce embeddings and layouts that are quite efficient often within constant factors of being optimal. However, even a modest constant factor may render an asymptotically optimal layout or embedding unacceptably inefficient in practice. This motivates the current paper. 2 ....

....network are complicated; they are not regular or recursive. The best known layout of the butterfly network with n inputs or outputs was due to Wise [20] with area 2n 2 . Recently, more compact layouts for the butterfly were found with area 11 6 n 2 [8] or n 2 o(n 2 ) [2]. However, the butterfly networks discussed in [2, 8, 20] are unfolded. To be fair, the folded butterfly network [13] should be used in comparison with the CCC. Generally, the corresponding areas of the folded butterfly using these layout schemes [2, 8, 20] are at least doubled. 4 Lower Bound on ....

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A. Avior, T. Calamoneri, S. Even, A. Litman, and A. L. Rosenberg. A tight layout of the butterfly network. In Proceedings of 8th ACM Symposium on Parallel Algorithms and Architectures, pages 170--175, 1996.

....aims at finding better layout schemes for the CCC. Research in the fields of graph embedding and VLSI layout has developed Correspondence: F.C.M. Lau, Department of Computer Science, The University of Hong Kong, Hong Kong. Email: fcmlau cs.hku.hk Fax: 852) 2559 8447. powerful techniques [2, 5] that can produce embeddings and layouts which are quite efficient often within a constant factor from the optimal. However, even a modest constant factor may render an asymptotically optimal layout or embedding unacceptable for real implementation. It is necessary to try to achieve the minimal. ....

....in [18] which is in terms of the bisection width of a graph. Lemma 1 [18] For any graph G with bisection width BW (G) AREA(G) BW (G) Gamma 1) 2 . The proof of the bisection width, 1 2 n, of CCC(n) however, is complicated. Alternatively, we can turn to the modified bounding strategy, from [2] where a lower bound of the butterfly network layout is proved by the same technique, but is in terms of the minimum special bisection width. Let G be a graph having a designated set of special nodes. The minimum special bisection width of G, denoted MSBW (G) is the smallest number of edges whose ....

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A. Avior, T. Calamoneri, S. Even, A. Litman, and A.L. Rosenberg. A tight layout of the butterfly network. Technical report, University of Massachusette, 1996.

....not difficult to show that the diameter of Bn is 2 logn, and the diameter of Wn is b#3logn#=2c,wherethediameter of a network is the maximum, over all pairs of nodes u and v, of the length, in terms of edges, of the shortest path between u and v. Also, the VLSI layout area of Bn is #1#o#1##n 2 [3] and the layout area of Wn is Q#n 2 #. Furthermore, the three dimensional layout volumes of Bn and Wn are Q#n 3=2 # [14] A network closely related to the butterfly is the cubeconnected cycles [8, 21] A log n dimensional cubeconnected cycles network CCC n consists of n cycles, each ....

A. Avior, T. Calamoneri, S. Even, A. Litman, and A. L. Rosenberg. A tight layout of the butterfly network. In Proceedings of the 8th ACM Symposium on Parallel Algorithms and Architectures, pages 170--175, June 1996.

....difficult to show that the diameter of Bn is 2 log n, and the diameter of Wn is b(3 log n) 2c, where the diameter of a network is the maximum, over all pairs of nodes u and v, of the length, in edges, of the shortest path between u and v. Also, the VLSI layout area of Bn is (1 Sigma o(1) n 2 [3] and the layout area of Wn is Theta(n 2 ) Furthermore, the three dimensional layout volumes of Bn and Wn are Theta(n 3=2 ) 12] A network closely related to the butterfly is the cube connected cycles [19] A log n dimensional cube connected cycles network CCCn consists of n cycles, each ....

A. Avior, T. Calamoneri, S. Even, A. Litman, and A. L. Rosenberg. A tight layout of the butterfly network. In Proceedings of the 8th Annual ACM Symposium on Parallel Algorithms and Architectures, pages 170--175, June 1996.

....difficult to show that the diameter of Bn is 2 log n, and the diameter of Wn is b(3 log n) 2c, where the diameter of a network is the maximum, over all pairs of nodes u and v, of the length, in edges, of the shortest path between u and v. Also, the VLSI layout area of Bn is (1 Sigma o(1) n 2 [3] and the layout area of Wn is Theta(n 2 ) Furthermore, the three dimensional layout volumes of Bn and Wn are Theta(n 3=2 ) 12] A network closely related to the butterfly is the cube connected cycles [19] A log n dimensional cube connected cycles network CCCn consists of n cycles, each ....

A. Avior, T. Calamoneri, S. Even, A. Litman, and A. L. Rosenberg. A tight layout of the butterfly network. In Proceedings of the 8th Annual ACM Symposium on Parallel Algorithms and Architectures, pages 170--175, June 1996.

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Avior, A., T. Calamoneri, S. Even, A. Litman, and A. Rosenberg, "A tight layout of the butterfly network," Proc. ACM Symp. Parallel Algorithms and Architectures, Jun. 1996, pp. 170-175.

No context found.

Avior, A., T. Calamoneri, S. Even, A. Litman, and A. Rosenberg, "A tight layout of the butterfly network," Theory Comput. Sys., vol. 31, no. 4, 1998, pp. 475-488.

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A. Avior, T. Calamoneri, S. Even, A. Litman, and A. Rosenberg. A tight layout of the butterfly network. In Proc. of the 8th ACM Symposium on Parallel Algorithms and Architectures (SPAA '96), pages 170--182, 1996.

No context found.

Avior, A., T. Calamoneri, S. Even, A. Litman, and A. Rosenberg, "A tightlayout of the butterfly network," Theory Comput. Sys., vol. 31, no. 4, 1998, pp. 475-488.

No context found.

A. Avior, T. Calamoneri, S. Even, A. Litman, and A. Rosenberg. A tight layout of the butterfly network. In 8th Annual ACM Symposium on Parallel Algorithms and Architectures (SPAA '96), pages 170--182, New York, USA, 1996. ACM.

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