| R. W. Hartenstein. (Invited paper): Trends in Recon gurable Logic and Recon gurable Computing. In Proceedings of the Ninth IEEE Int. Conf. on Electronics, Circuits and Systems - ICECS 2002. |
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R. W. Hartenstein. (Invited paper): Trends in Recon gurable Logic and Recon gurable Computing. In Proceedings of the Ninth IEEE Int. Conf. on Electronics, Circuits and Systems - ICECS 2002.
.... are needed (the one for the run time operation and the other for the processor recon guration) Two kinds of machine paradigms have to be explored: recon gurable instruction stream processors as well as data stream processors based on very powerful recon gurable data path arrays (rDPUs) [7]. Working on data stream processors also includes distribuited memory architectural exploration. This all is of great interest, since no simulation is possible over standard hardware description languages such as Verilog and VHDL. For discriminating these two layers higher order rewriting logic ....
R. W. Hartenstein. (Invited paper): Trends in Recon gurable Logic and Recon gurable Computing. In Proceedings of the Ninth IEEE Int. Conf. on Electronics, Circuits and Systems - ICECS 2002.
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