R. Alur and D. L. Dill. A theory of timed automata. Theor. Comput. Sci., 126(2):183--235, 1994. Home/Search Document Details and Download
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Counter Machines: Decidable Properties and.. - Ibarra, Su, Dang.. (2000) (5 citations) (Correct)
....that strong reversal boundness restricts the behavior of a counter too much, since changing from a strictly increasing (or decreasing) mode to a no change mode counts as a reversal. However, if the counters behave like clocks which either increase with rate 1 or reset to 0 as in timed automata [1], strong reversal boundness is equivalent to reversal boundness. Using this observation and the results in this paper, we are able to show a number of results on clocked systems with parameterized durations [4] binary reachability characterization of discrete timed pushdown automata [5] and ....
R. Alur and D. Dill. "A theory of timed automata," Theo. Comp. Sci., 126(2):183-235, 1994.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI).. - Kenneth Stevens Senior (Correct)
....transistors and gates. 3) Relative Timing Verification: This section introduces the method developed to verify a large, relative timed asynchronous circuit called RAPPID [1] An implementation conforms to a specification when an implementation is an acceptable construction of the specification [16], 27] 34] In this section, implementations can be assumed to be parallel compositions of the untimed behavioral specifications of the gates. Relative timing predicates can be added to implementations and specifications to reduce their concurrency by pruning states in a state graph (SG) that ....
R. Alur and D. L. Dill, "A theory of timed automata," Theoret. Comput. Sci., vol. 126, no. 2, pp. 183--235, 1994.
Correctness and Reduction in Timed Circuit Analysis - Mercer (2002) (Correct)
....to find several di#erent ways to model a timed system; each one has its strengths and weaknesses 40 according to the goal it is trying to achieve. The myriad of existing models makes selecting an appropriate model challenging. Alur introduces timed automata as a signal model for timed systems in [18]. A timed automaton is a state based specification language where transitions between states are governed not only by Boolean functions defined over inputs, but clock valuations too. An example of a timed automaton model of the function c = a is shown in Fig. 2.17(a) Each node of the automaton ....
....of general properties. A model is often specified in a temporal logic such as LTL in [45] or CTL in [46, 47, 48] and it models behaviors that the circuit should uphold. To specify timed behaviors, it is necessary to use a more complex and expressive timed temporal logic such as those presented in [49, 50, 51, 18, 52]. With any temporal logic, the circuit is framed in an underlying representation that captures essential behaviors in the circuit. A circuit is then shown to satisfy a model by exploring all behaviors allowed in the underlying representation. If a behavior is allowed in the circuit but not ....
R. Alur and D. L. Dill, "A theory of timed automata," Theoretical Computer Science, vol. 126, no. 2, pp. 183--235, 1994.
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....with a popular timing framework for determining the causality of messages in distributed systems, called vector clocks. 1. Introduction There exist several models for incorporating time into the description of the behavior of discrete event systems (e. g, 3, 9] and timed automata (e.g. [1, 2, 7]) We are interested in two issues concerning timed discrete event systems: i) decentralized models (with partial observation) that utilize time (and no global clock is available) and (ii) modelling asynchronous communication between decentralized agents. To examine (i) we use the notion of ....
R. Alur and D. Dill. A theory of timed automata. Theoretical Comp. Science, 126:183-235, 1994.
Characteristic Formulae for Timed Automata - Aceto.. (2000) (1 citation) (Correct)
....formula. The resulting algorithm o#ered in [9] is still considered to be one of the most e#cient for checking behavioural preorders. In the setting of modelling and verification for real time systems, a characteristic formula construction for timed bisimulation equivalence over timed automata [2] has been o#ered in [19] In op. cit. Laroussinie, Larsen and Weise have proposed the logic L # a real time version of Hennessy Milner Logic [14] with greatest fixed points , and have shown that its associated model checking problem is decidable, and that this logic is su#ciently expressive ....
....blow up involved in the characteristic formula construction from op. cit. is due to the fact that the formula is essentially constructed by applying the standard, untimed construction developed by Ing olfsd ottir, Godskesen and Zeeberg [15] to the region graph associated with the timed automaton [2]. As shown by Alur and Dill [2] the size of the region graph is exponential in that of the original timed automaton. This study o#ers characteristic formula constructions for timed automata using the logic L # that, like those in the untimed setting and unlike that o#ered in [19] yield formulae ....
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R. Alur and D. L. Dill, A theory of timed automata, Theoretical Comput. Sci., 126 (1994), pp. 183--235. Fundamental Study.
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....to include simple continuous dynamics: these include timed target set initial set form ds reaChhabile Figure 1: Difference between backwards and forwards reachable sets. rb. iunsafe ] target set nsafe initiaJization Figure 2: Using the backwards reachable set to verify safety. automata [21], linear hybrid automata [22, 23, 24, 25] and hybrid input output automata [26] 2.2 Safety Verification Much of the research in hybrid systems has been motivated by the need to verify the behavior of safety critical system components. The problem of safety verification may be encoded as a ....
R. Alur and D. Dill, "A theory of timed automata," Theoretical Computer Science, vol. 126, pp. 183-235, 1994.
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....Notes in Theoretical Computer Science 89 No. 2 (2003) URL: http: www.elsevier.nl locate entcs volume89.html 20 pages Testing and Monitoring Model based Generated Program Li Tan, Jesung Kim, and Insup Lee 1,2 Department of Computer and Information Science University of Pennsylvania Philadelphia, PA USA Abstract We propose an integrated ....
....be introduced by manual translation. Recently, code generation from hybrid system models has been used for embedded systems. Industry has followed the trend by providing their own tools This research was supported in part by NSF CCR 9988409, NSF CCR 0086147, NSF CCR 0209024, ARO DAAD19 01 1 0473, and DARPA ITO MOBIES F33615 00 C 1707. Email: tanli,jesung saul.cis.upenn.edu Email: lee cis.upenn.edu c #2003 Published by Elsevier Science B. V. environment constraints testing goal coverage checker simulator code generator .cc .cc .cc code tester monitor model testing ....
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....to determine which input events are consumed by the program at each reaction. The real time system consists of the compiled program and the event handler, which are composed with the environment that produces the inputs. Conceptually, the behavior of each component is modeled as a timed automaton [3], and the model of the overall system is obtained by an appropriate composition operator. To extract a timed model from the application software, we assume that time elapses only when the program is executing the data manipulation functions written in C. These functions are annotated with ....
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