M. Ayala-Rincon, R. M. Neto, R. Jacobi, C. Llanos, and R. W. Hartenstein. Applying ELAN Strategies in Simulating Processors over Simple Architectures. In B. Gramlich and S. Lucas, editors, Proc. 2 nd Workshop on Reduction Strategies in Rewriting and Programming, ENTCS volume 70(6):16 pages. Elsevier 2002. Home/Search Document Not in Database Summary Related Articles Check |
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Architectural Speci - Cation Exploration And (2002) Self-citation (Ayala-rinc Neto Jacobi Llanos Hartenstein) (Correct)
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M. Ayala-Rincon, R. M. Neto, R. Jacobi, C. Llanos, and R. W. Hartenstein. Applying ELAN Strategies in Simulating Processors over Simple Architectures. In B. Gramlich and S. Lucas, editors, Proc. 2 nd Workshop on Reduction Strategies in Rewriting and Programming, ENTCS volume 70(6):16 pages. Elsevier 2002.
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M. Ayala-Rincon, R. M. Neto, R. Jacobi, C. Llanos, and R. W. Hartenstein. Applying ELAN Strategies in Simulating Processors over Simple Architectures. In 2 nd Workshop on Reduction Strategies in Rewriting and Programming, 2002.
Architectural Specification, Exploration and.. - Ayala-Rincon.. (2002) Self-citation (Ayala-rinc Neto Jacobi Llanos Hartenstein) (Correct)
....basic processor 5 Itb stands for instruction template bu er (ITB) and t s and v s for either a tag or a value. mf is the memory ag that can be dispatched (D) or is waiting to be dispatched (U) The complete set of rewriting rules for the speculative processor implemented in ELAN is given in [3]. Here we explain the operational semantics of three of these rules: PsOp, PsJzIssue and PsJumpCorrectSpec, whose speci cation is given in the Table 2. PsOp] Sys(m,Proc(ia,rf,ITB(ia1,k,t(k) Op(v,v1) wf,sf) itbs2, btb, prog) Sys(m,Proc(ia,rf,ITB(ia1,k,t(k) execOponval(v,v1) wf,sf) itbs2, ....
....correctly or if the processor needs to x the mistake and restart the execution at the correct program counter value, simply by ignoring the remaining instructions already in the ITB. The rules PsJumpCorrectSpec, PsJumpWrongSpec, PsNoJumpCorrectSpec and PsNoJumpWrongSpec deal with this issue (see [3]) Exemplifying, lets say the head of the ITB is of the form ITB(ia,k,Jz(v,nia) wf,Spec(pia) the rule has to check whether the value v is zero or not and then, respectively, check whether either the speculated address pia coincides with nia or with ia 1. In this event the prediction has been ....
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M. Ayala-Rincon, R. M. Neto, R. Jacobi, C. Llanos, and R. W. Hartenstein. Applying ELAN Strategies in Simulating Processors over Simple Architectures. In B. Gramlich and S. Lucas, editors, Proc. 2 nd Workshop on Reduction Strategies in Rewriting and Programming, ENTCS volume 70(6):16 pages. Elsevier 2002.
Efficient Computation of Algebraic Operations over .. - Ayala-Rincon.. (2003) Self-citation (Ayala-rincn Jacobi Llanos Hartenstein) (Correct)
.... systems [26] Also we have contributed in this field by showing how rewriting theory can be applied for the specification of processors over simple architectures (as Arvind s group does) as well as for the purely rewrite based simulation, verification and analysis of the specified processors [3]. To achieve this we applied rewriting logic that extends the pure rewriting paradigm allowing for a logical control of the application of the rewriting rules by strategies [21,7] Important programming environments based on the rewriting logic paradigm are ELAN [9,7] Maude [21,8] and Cafe OBJ ....
.... digital circuits is nothing new [11] But in our rewriting logic based setting, we showed how one can naturally profit from the discrimination between rewriting and logical strategies to simplify the purely rewrite based specification, experimentation, simulation (and even verification [3]) of reconfigurable systems. By rewriting logic even the sophisticated dynamical reconfiguration appears a very natural mechanism to be simulated via logical strategies. Since digital systems get more and more complex, modeling the various architectural trade offs in the context of reconfigurable ....
M. Ayala-Rincn, R. M. Neto, R.P. Jacobi, C. H. Llanos and R. W. Hartenstein, Applying ELAN Strategies in Simulating Processors over Simple Architectures. In B. Gramlich and S. Lucas Eds., Reduction Strategies in Rewriting and Programming, ENTCS 70(6):20 pages, 2002.
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