D. K. Pradhan, Fault-Tolerant Computing: Theory and Techniques. Englewood Cliffs, NJ: Prentice-Hall, 1986.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....with CED have the capability to detect both temporary and permanent faults and are widely used in systems where dependability and data integrity are of importance. While e#cient schemes have been developed for CED in circuits with regular structures, e.g. adders [Gorshe 96] multipliers [Pradhan 86] and PLAs [Boudjit 93] and while most memory elements use CED based on error detecting and error correcting codes [Chen 84] CED techniques for multilevel logic circuits have received less attention for two reasons: i) The very high overhead (power, area, timing, etc. associated with ....

D. K. Pradhan, Fault Tolerant Computing -- Theory and Techniques, Vol. 1, Prentice-Hall, 1986.

....[32] It is well known that a one step t diagnosable system must satisfy the following two constraints: a. There must be at least 2t 1 nodes in the system. b. Each node must be diagnosed by at least t other nodes. Before we proceed further, we recapitulate the definition of a D ffi;t system [33, 34]. Definition 1 A D ffi;t system is a directed graph G = V; E) where an edge e ij 2 E exists from a vertex v i 2 V to a vertex v j 2 V if and only if j = i ffim) mod n where n is the number of vertices in G, ffi is an integer, and m = 1; 2; t. It is well known [33, 34] that for a ....

....a D ffi;t system [33, 34] Definition 1 A D ffi;t system is a directed graph G = V; E) where an edge e ij 2 E exists from a vertex v i 2 V to a vertex v j 2 V if and only if j = i ffim) mod n where n is the number of vertices in G, ffi is an integer, and m = 1; 2; t. It is well known [33, 34] that for a class of D ffi;t systems with n = 2t 1 and in which ffi and n are relatively prime, the conditions for t fault diagnosability stated above are not only necessary but also sufficient if we assume that the vertices of the graph represent the processing nodes in the system and the edges ....

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D. K. Pradhan, Fault-Tolerant Computing: Theory and Techniques, Vol. II, Englewood Cliffs, NJ: Prentice Hall, 1986.

....be detected by a timeout. To guarantee that we observe any illegal codewords on the output of the circuit we must only guarantee that each gate generates an illegal output encoding in response to any illegal input encoding. While many other self checking codes and architectures have been proposed [18], it is not clear that any of them o#er the possibility of easily balancing the power dissipation for di#erent data inputs. A1 A0 meaning 0 0 clear 0 1 logical 0 1 0 logical 1 1 1 alarm Figure 1. Dual rail encoding with alarm signal defined Ideally all detectable faults would now produce ....

D. K. Pradhan, Fault Tolerant Computing: Theory and Techniques, vol. 1. Prentice-Hall, 1986.

....nodes returned by the checking algorithm (See Lemma 3) Synchronize: The second step in the secured link state protocol lies in the synchronization of the topology among the neighbors. The synchronization is carried out using the principle of voting used in N Modular Redundancy (NMR) systems [23] [25]. Following are the steps involved in the synchronization process: 1. Each node receives topology information from each of its neighbors. 2. For each entry i of the adjacency matrix (Adj) comparison is made with the i entry of the topology information obtained from each of the neighbors. 3. ....

D. K. Pradhan, "Fault-Tolerant Computing - Theory and Techniques, " Prentice Hall, vol. 2, 1986.

....state (see Figure 1) To guarantee that we observe any illegal codewords on the output of the circuit we must only guarantee that each gate generates an illegal output encoding in response to any illegal input encoding. While many other self checking codes and architectures have been proposed [15], it is not clear that any of them o#er the possibility of easily balancing the power dissipation for di#erent data inputs. A1 A0 meaning 0 0 clear 0 1 logical 0 1 0 logical 1 1 1 alarm Figure 1. Dual rail encoding with alarm signal defined Ideally all detectable faults would now produce ....

D. K. Pradhan, Fault Tolerant Computing: Theory and Techniques, vol. 1. Prentice-Hall, 1986.

....with reliability engineering research, and are also used in hardware design packages to permit direct instantiation of their design as a complete system netlist. Faults are represented and analysed through the use of fault models at both the gate and functional level within an electronic system [4]. Gate level fault models describe the effect of an error in terms of individual logic gates and their connections. Functional fault models check the entire function of a system at once, under the premise that if the functionality is correct, then the system under test is fault free. The work ....

D.K.Pradhan, Fault Tolerant Computing: Theory and Techniques - Volume 1, Prentice-Hall, 1986.

.... real time multiprocessor systems, dependability can be provided by scheduling multiple copies of tasks on different processors 6,7,8] Primary backup copies (PB) and triple modular redundancy (TMR) are two basic methods that allow multiple copies of a task to be scheduled on different processors [9]. Example of PB scheme can be found in [10] We have explored algorithms using PB approach to schedule dependable real time tasks with non dependable real time task [11, 12] Balaji has studied an algorithm to dynamically distr ibute the workload of a failed processor to other operable processor ....

D.K. Pradhan. Fault Tolerant Computing: Theory and Techniques. JN: Prentice-Hall. 1986.

....systems, such as PDAs and mobile phones, however, battery life time is also an important quality factor. x Safety Many embedded applications such as automotive electronics or avionics have safety requirements. There is a host of work in self checking and fault tolerant electronic systems design [4, 5] but, in embedded systems, mechanical parts must be regarded as well. Safety requirements can have very subtle effects on system design when we take EMI (electromagnetic integrity) into account [6] As an example, the clock frequency may be constrained since (differential mode) radiation of a ....

Pradhan, D.K. (1986) Fault Tolerant Computing Theory and Techniques I and II. Prentice-Hall.

....and recovering from that failure. Traditionally, these fault tolerance actions are performed in the hardware, operating or database systems used in the underlying layers of the application software. Hardware fault tolerance is provided using Duplex, Triple ModuleRedundancy or other techniques [Pra86]. Fault tolerance in the operating and database layers is often provided using replicated file systems [Sat90] exception handling [Shr85] disk shadowing [Bit88] transaction based checkpointing and recovery [Nan92] and other system routines. These methods and technologies handle faults ....

D. K. Pradhan (ed.). Fault-Tolerant Computing: Theory and Techniques, volumes 1 and 2, Prentice-Hall, 1986.

....faults in the branches of the interconnections are not covered. Further, the analysis of the fault coverage is based on the logic equations of the divider and have not a general validity as the results obtained here for single and multiple cell fanout networks. This design is also reported in [PRA86] and is illustrated for a 5 bit divisor. Again this design is not fault secure for the same reasons. PRA86] also aplies the design methodology of [FUR83] in the case of carry lookahead adders and on the Braun multiplier, but not analysis of the fault secureness is reported. Nevertheless the ....

....is based on the logic equations of the divider and have not a general validity as the results obtained here for single and multiple cell fanout networks. This design is also reported in [PRA86] and is illustrated for a 5 bit divisor. Again this design is not fault secure for the same reasons. [PRA86] also aplies the design methodology of [FUR83] in the case of carry lookahead adders and on the Braun multiplier, but not analysis of the fault secureness is reported. Nevertheless the parity prediction scheme can not achieve fault secureness for carry lookahead adders. IV. CONCLUSIONS In this ....

Pradhan D.K., "Fault Tolerant Computing, Theory and Techniques", Volume I, Prentice Hall, Englewood Cliffs, New Jersey, 1986.

....Shortest Path Routing: In [10] algorithms to obtain a shortest path in a product network from the shortest path algorithms of the factor networks are given. This section studies the specific algorithm for the MCT . The algorithm to find a shortest path in a complete binary tree can be found in [7]. The algorithm to find the shortest path in MCT r (N ) is a simple extension of this algorithm for T (h) The shortest path from any node x to any node y in MCT r (N ) is obtained by simply applying the shortest path routing algorithm described for the tree T (h) along each dimension where the ....

D. K. Pradhan, ed., Fault-Tolerant Computing: Theory and Techniques, vol. 2, ch. 7. Englewood Cliffs: Prentice Hall, 1986.

....as defined in Section 2. The root of T (h) is labeled 1. For any internal node labeled u, its left child is labeled 2u and its right child is labeled 2u 1. Based on these labels, a simple algorithm to find the first edge of the shortest path from a vertex u to a vertex v, u 6= v, can be derived [16]. Let u b and v b be the binary representations of the labels assigned to u and v, respectively, where leading zeroes have been removed. If u b is not a prefix of v b , the first edge of the path from u to v connects u with its parent vertex. If u b is a prefix of v b , then remove these bits from ....

D. K. Pradhan, ed., Fault-Tolerant Computing: Theory and Techniques, vol. 2, ch. 7. Englewood Cliffs: Prentice Hall, 1986.

....the circuits, rigorous testing of hardware components, and periodic preventive maintenance of the operational system in order to remove faults before they cause errors. Examples of hardware fault tolerance techniques are the use of error detection and correction codes, and instruction retry [Pra86] Fault prevention techniques commonly used in the design and development of software layers are the use of top down software design [Som92] structured programming [DDH72] program verification [Gri81] software walk throughs [Zie83] and software development tools [Fis91] All these techniques ....

D. K. Pradhan, editor. Fault-Tolerant Computing: Theory and Techniques, volume 1 and 2. Prentice-Hall, 1986.

....the functional level is efficient and represents the preferred level of abstraction for testing. This paper explores the nature of functional faults and tests, and their relation to low level faults. Others have noted the advantages of defining high level fault models that detect physical faults [1,12], but prior analysis is ad hoc and is not applied to large circuits. Here, we present a new high level fault model called the physically induced fault model. If gate level SSL faults are considered with this model, complete functional fault detection can guarantee complete SSL fault detection. We ....

D. K. Pradhan, Ed., Fault-Tolerant Computing Theory and Techniques, Vol. I, Prentice-Hall, Englewood Cliffs, NJ, 1986.

....to tolerate the NP completeness of the test generation problem are not available. Yet this group of algorithms serves the very important purpose of enlightening the fundamental nature of testing problems. J. A. Abraham and V. K. Agarwal, Fault Tolerant Computing Theory and Techniques [Pra86] The Boolean difference is not used directly for practical test pattern generation. The usefulness of the Boolean difference is as a tool for theoretical studies of testing and checking methods. E.J. McCluskey, Logic Design Principles [McC86] For all but very simple networks the ....

D. K. Pradhan. Fault-Tolerant Computing Theory and Techniques. Prentice-Hall Publishing, 1986.

....the phase that tasks are submitted accepted to the system. Clearly, accounting for recovery from faults is an essential requirement of HRTSs. When dealing with such HRTSs, permanent faults can be tolerated by using hot standby spares [KS86] or they can be masked by modular redundancy techniques [Pra86]. In addition to permanent faults, tolerance to transient faults is very important, since it has been shown to occur much more frequently than permanent faults [IR86, IRH86, CMS82] In a study, an orbiting satellite containing a microelectronics test system was used to measure error rates in ....

D.K. Pradhan. Fault Tolerant Computing: Theory and Techniques. Prentice-Hall, NJ, 1986.

....to be subverted. Even if they can fail, redundancy can prevent malfunction. In security, however, if the one mechanism can be broken then its identical partner can also be broken. The critical difference is malicious attack versus random failure. As for software fault tolerance, according to [169] no major body of theory yet exists. Of course, fault tolerant software systems are still successfully designed, employing techniques such as fault avoidance (since many software faults are due to design errors) and redundancy techniques analogous to replicated hardware. The latter are difficult ....

Pradhan, D. Fault-Tolerant Computing: Theory and Techniques. PrenticeHall, 1986.

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D. K. Pradhan, Fault-Tolerant Computing: Theory and Techniques. Englewood Cliffs, NJ: Prentice-Hall, 1986.

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D.K. Pradhan, Fault Tolerant Computing: Theory and Techniques, vol. 1, Prentice-Hall, Englewood Cliffs, NJ, 1986.

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Pradhan, D.K., Fault Tolerant Computing: Theory and Techniques, Vol I and II, Prentice Hall, Englewood Cliffs, 1986.

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PRADHAN D. "Fault Tolerant Computing : Theory and Techniques", Prentice Hall 1986.

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D. K. Pradhan, Fault-Tolerant Computing Theory and techniques. New Jersey: Prentice Hall, 1983

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Pradhan, D. K., Chapter 5, Fault Tolerant Computing -- Theory and Techniques, Vol. 1, Prentice-Hall, NJ, 1986.

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Dhiraj K. Pradhan. Fault-Tolerant Computing: Theory and Techniques, volume I. Prentice-Hall, Inc., 1986.

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D.K. Pradhan, Fault-Tolerant Computing -- Theory and Techniques, Volumes I and II, Prentice-Hall, Englewood Cliffs, N.J., 1986.

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