Erik Jan Marinissen, Vikram Iyengar, and Krishnendu Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. In Proc. IEEE International Test Conference (ITC), pages 519--528, Baltimore, MD, October 2002.  Home/Search Document Details and Download
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Layout-Driven SOC Test Architecture Design for Test Time and .. - Goel, Marinissen (2003) Self-citation (Marinissen) (Correct)
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Erik Jan Marinissen, Vikram Iyengar, and Krishnendu Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. In Proc. IEEE International Test Conference (ITC), pages 519--528, Baltimore, MD, October 2002.
Efficient Modular Testing of SOCs Using Dual-Speed TAM.. - Anuja Sehgal And Self-citation (Chakrabarty) (Correct)
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E. J. Marinissen, V. Iyengar and K. Chakrabarty. A set of benchmarks for modular testing of SOCs. Proc. Int. Test Conf., pp. 519-- 528, 2002.
SOC Test Planning Using Virtual Test Access Architectures - Sehgal, Iyengar, Chakrabarty (2004) Self-citation (Iyengar Chakrabarty) (Correct)
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E. J. Marinissen, V. Iyengar and K. Chakrabarty. A set of benchmarks for modular testing of SOCs. Proc. Int. Test Conf., pp. 519--528, 2002.
Test Access Mechanism Optimization, Test Scheduling, .. - Iyengar.. (2003) Self-citation (Marinissen Iyengar Chakrabarty) (Correct)
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E.J. Marinissen, V. Iyengar, and K. Chakrabarty, "A Set of Benchmarks for Modular Testing of SOCs," Proc. Int'l Test Conf., pp. 519-528, 2002. (Benchmarks available at http://www.extra. research.philips.com/itc02socbenchm).
A Partition-Based Approach for Identifying Failing Scan.. - Liu, Chakrabarty (2003) Self-citation (Chakrabarty) (Correct)
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E. J. Marinissen, V. Iyengar and K. Chakrabarty, "A Set of Benchmarks for Modular Testing of SOCs", Proc. Int. Test
Recent Advances in Test Planning for Modular Testing .. - Iyengar.. (2002) Self-citation (Marinissen Iyengar Chakrabarty) (Correct)
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E.J. Marinissen, V. Iyengar and K. Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. Proc. Int. Test Conf., 2002, to appear. (Benchmark SOC data available at http://www.extra.research.philips.com/itc02socbenchm)
A Partition-Based Approach for Identifying Failing Scan.. - Liu, Chakrabarty Self-citation (Chakrabarty) (Correct)
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E. J. Marinissen, V. Iyengar and K. Chakrabarty, "A Set of Benchmarks for Modular Testing of SOCs", Proc. Int. Test
Test Cost Reduction for SOCs Using Virtual TAMs.. - Sehgal, Iyengar.. (2003) Self-citation (Iyengar Chakrabarty) (Correct)
....results on core assignment and TAM optimization using virtual TAMs. We demonstrate that the SOC testing time and therefore implicit test cost can be significantly reduced using virtual TAMs. Experimental results are presented for three benchmark SOCs from the ITC 02 SOC Test Benchmarks suite [14]. In Table 2, we present results on the testing times obtained for different values of TAM width using virtual TAMs. The testing time is measured in terms of the number of scan clock cycles. The total number of high frequency and low frequency ATE pins used for test is denoted by #### . Therefore ....
E.J. Marinissen, V. Iyengar and K. Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. Proc. Int. Test Conf., pp. 519--528, 2002.
Defect Prob393427597922 System-On-Chip Test Scheduling - Eriklarsson Julien Pougetan (Correct)
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E. J. Marinissen, V. Iyengar, and K. Chakrabarty, "A Set of Benchmarks for Modular Testing of SOCs", Proceedings of International Test Conference (ITC), pp. 519-528, Baltimore, MD, USA, October 2002.
Power-aware NoC Reuse on the Testing of Core-based Systems - Cota, Carro, Wagner.. (2002) (1 citation) (Correct)
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E. J. Marinissen, V. Iyengar, and K. Chakrabarty. A Set of Benchmarks for Modular Testing of SOCs. In International Test Conference, pages 521--528, Oct. 2002.
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