| P. T. Krein, Elements of Power Electronics. New York: Oxford University Press, 1998, p. 556. |
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P. T. Krein, Elements of Power Electronics. New York: Oxford University Press, 1998, p. 556.
....extra clock cycles are inserted as margins in each pulse period, and therefore the actual counter clock frequency is 352.8 kHz # ### # ##### MHz. The logic counter also is used to generate dead times that ensure break before make (BBM) switch operation and avoid shoot through currents [33] in the power stage. Fig. 6 shows the PWM inverter power stage. It is a conventional full bridge complementary MOSFET inverter followed by a passive low pass filter. Level shifting circuitry is used for the high side gate drivers. There is nothing special about the devices our experimental ....
P. T. Krein, Elements of Power Electronics. New York: Oxford University Press, 1998, p. 556.
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