L. George and A. W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....11 ffl spill code inserts spill instructions to spill the nodes so identified in the select phase. This is the allocator on which we ran all of the experiments in the rest of this thesis. We chose not to include some recent enhancements such as George and Appel s iterated copy coalescing [24] and Bergner et al. s interference region spilling [5] because we are not confident that they have received widespread implementation as yet. When we explain our results, we will mention how some of these enhancements might affect those results. 2.6 Previous work Register allocation is a ....

.... spilling such as live range splitting and rematerialization [7, 11] More recent work of particular interest includes George and Appel s work on iterated register coalescing, in which they attempt to reduce the register pressure by folding copy operations during the simplify phase of the compiler [24]. Their ideas seem to be only efficacious in specific contexts, and may not be significantly helpful in general. Our implementation of their algorithm suggested that its improvements occur mainly in an environment of a high proportion of copy instructions relative to the total number of ....

Lal George and Andrew W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.

....that address these problems can increase the demand for registers and provoke the register allocator to spill more values to memory. The perceived increase in the cost of spilling, due to more spills and longer memory latencies, has led to a spate of recent research on reducing spill costs (e.g. [16, 3, 12]) Register spills are problematic for two reasons. First, they add loads, stores, and address computations to the program, each of which must be scheduled, fetched, and executed. Second, they perturb the behavior of the data AccordingtoUptonet al... the cost of a 1 KB cache is negligible [26] ....

Lal George and Andrew W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.

....EMPHCP (b) Table 1. Sequence of heuristics used by the convergent scheduler for (a) the Rawmachine and (b) clustered VLIW. high level structure. Like Rawcc, it is implemented on top of Machsuif. It rst performs space time scheduling, followed by traditional single cluster register allocation [8]. Both Rawcc and the Chorus compiler employ congruence transformation and analysis to increase and analyze the predictability of memory references [13] This analysis creates preplaced memory reference instructions that must be placed on speci c tiles or clusters. For dense matrix loops, the ....

L. George and A. W. Appel. Iterated Register Coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300-324, 1996.

....high level program. The compiler also performs optimisations such as dead code elimination, copy propagation, constant propagation, common sub expression elimination and loop invariant code hoisting [15, 16] Commonly used variables are allocated to registers, using iterated register coalescing [17]. A simple example of the result of compiling a code fragment for the processor is shown in Figure 4. 5.1 Results Using the compiler and the cycle accurate processor simulator, we conducted a range of experiments in compiling and executing simple benchmarks. These benchmarks included selected ....

Lal George and Andrew W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.

.... 2 fun applyf (f, n) let fun lp i i = if (i n) then let fun lp j j = if (j n) then (f(i, j) lp j(j 1) else ( in lp j 0; lp i(i 1) end else ( in lp i 0 end Figure 1: A nested loop using tail recursion translate it to assembly code using the MLRISC framework [GGR94, GA96] Each BOL cluster is mapped to a single machine procedure, i.e. its fragments share the same stack frame at run time. Furthermore, control transfers inside the cluster are implemented as jumps and local variables, including internal fragment parameters, are mapped to MLRISC pseudo registers. ....

George, L. and A. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3), May 1996, pp. 300--324.

.... By using a calling convention that passes arguments and results in registers, and a register allocation technique Sven Olof Nystrom, Johan Runeson and Jan Sjodin: Code Compression Techniques for Embedded Systems 9 that reduces the number of register to register copies through coalescing [8], we expect that the overhead of procedure calls can be kept low. To reduce the overhead of saving and restoring registers at procedure calls, it will probably be worthwhile to consider an interprocedural register allocation technique [1,17,16,10] An ambitious compiler for an embedded processor ....

Lal George and Andrew W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.

.... This report describes the design and implementation of the new register allocator for the MLRISC customizable code generator [Geo97] This new allocator, like the current allocator distributed with MLRISC, is a Chaitin style graph coloring allocator that uses the iterated coalescing algorithm [GA96] The new allocator, however, has a di#erent client interface, uses di#erent data structures, and has incorporated the following new features and improvements. Priority Modern compiler optimizations are often driven by execution frequency information gathered either through profiling or static ....

....one sources and destinations, we also associate a copy temporary tmp with the copy instruction. During code emission a parallel copy has to be linearized to a sequence of actual instructions. This copy temporary is used for shu#ing values if the linearization contains cycles. George and Appel [GA96] and Reig Galilea and George [GG99] described how paralell copies can be used to aid code generation for SML and C [JON98, JNON97] 2.3 Phases in the allocator Figure 1 shows the phase ordering of the iterated coalescing framework [GA96] used in the allocator. Phases surrounded by dashes are ....

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L. George and A. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3), May 1996.

....of the procedural abstraction optimization is sensitive to the cost of procedure calls. By using a calling convention that passes arguments and results in registers 1 and a register allocation technique that reduces the number of register to register copy instruction through coalescing [6], we expect that the overhead for procedure calls can be kept low. 1. Note that the new procedures are never called from external sources, which means we can safely use our own non standard calling convention for them. Code Compression through Procedural Abstraction before Register Allocation8 ....

Lal George and Andrew W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300-324, May 1996.

....passing and value return explicit as moves between physical locations and pseudo registers. 2. The second phase eliminates unnecessary register moves by coalescing pseudo registers. It coalesces registers aggressively and does not use the more conservative heuristics suggested by [BCT94, GA96] The phase rewrites the intermediate form after each pass of coalescing and iterates until no register coalesces occur. 3. The third phase, which is performed lazily, estimates the cost of spilling each pseudo register. It sums all occurrences of each pseudo register, weighting each occurrence ....

Lal George and Andrew W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.

....do not share an edge in the interference graph, the corresponding nodes can be coalesced into one, and the move eliminated. Unfortunately, aggressive coalescing can lead to uncolorable graphs, in which additional live ranges need to be spilled to memory. More recent work on graph coloring ( 10] [36]) has focused on removing unnecessary moves in a conservative manner so as to avoid introducing spills. Some simpler heuristic solutions also exist for the global register allocation problem. For example, lcc [31] allocates registers to the variables with the highest estimated usage counts, ....

....two UNIX utilities. As before, linear scan register allocation is compared against a graph coloring algorithm and the simple algorithm based on usage counts. It is also compared against second chance binpacking [73] The graph coloring allocator is an implementation of iterated register coalescing [36] developed at Harvard. For completeness, this section also reports the compile time performance of the SUIF implementation of binpacking and linear scan in Section 5.2.3, even though the underlying SUIF infrastructure has not been designed for efficient compile times. All benchmarks were compiled ....

L. George and A. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.

....Call the procedure at the address formed by evaluating expression addr. copy dst, src Copy the registers listed in src into the corresponding registers listed in dst ; this is a parallel operation: no register can appear more than once in the union of src and dst. copy statements are coalesced [9] by MLRISC whenever possible. mv dst, exp Move the result of evaluating expression exp into register dst. jmp addr Jump to the code at the address formed by evaluating expression addr. ret Return from the current procedure. store32 addr, exp Store the result of evaluating expression exp as a ....

....pseudo code, this is likely to be difficult for a back end that performs aggressive optimizations (e.g. global instruction scheduling) The shape of the mapping to machine registers can also present problems to the implementor. MLRISC maps each pseudo register to at most one machine register [9]; thus, when an unspilled pseudo register is live across a call site, we can always precisely identify which machine register it is mapped to. If a single pseudo register might be mapped to one of several machine registers at different points in the code, then MLRISC would need to tell us the ....

Lal George and Andrew W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.

.... and deficits depending on the application domain (we have already mentioned in the introduction our criteria for choosing SCCS) There are also a variety of formalisms for specifying asynchronous and or synchronous concurrent systems [Mil89] including Petri Nets, CCS, SCCS, ACP, CIRCAL, and CSP [Mil89, Mil93, Hoa85, Mil85, BRR87, Dav90]. Process algebra has been used to give a semantics to a communications protocol language, LOTOS; a parallel object oriented language, POOL; a computer integrated manufacturing system; and to the specification of low level digital hardware; these and other applications of process algebra may be ....

.... algebra has been used to give a semantics to a communications protocol language, LOTOS; a parallel object oriented language, POOL; a computer integrated manufacturing system; and to the specification of low level digital hardware; these and other applications of process algebra may be found in [Mil85, Bae90, Bri88]. Of the formalisms, all except CIRCAL are for specifying asynchronous systems. CIRCAL is similar to SCCS, and our choice of SCCS is largely pragmatic: there is a large body or research to draw upon for doing formal analysis, and there are also tools available. There has been some research into ....

George Milne. CIRCAL and the representation of communication, concurrency, and time. ACM Transactions on Programming Languages and Systems, 7(2):270--298, April 1985.

....modified the coalescing phase so that it never coalesces any register copy that has been inserted as split code. This restriction may be relaxed a little by allowing Briggs conservative coalescing [5, Page 49] or removed completely using George and Appel s Iterated Register Coalescing technique [13]. These techniques allow two live ranges to be coalesced, only if they can guarantee that the new larger live range is colorable. 4.5 Comparison to Priority Based Coloring Now that we have described our interference region splitting technique, it would be interesting to compare it with other ....

Lal George and Andrew W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.

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L. George and A. W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.

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Lal George and Andrew W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300324, May 1996.

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L. George and A. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(5), May 1996.

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L. George and A. W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.

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L. George and A. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3), May 1996.

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Lal George and Andrew W. Appel. Iterated Register Coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300--324, May 1996.

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Lal George and Andrew W. Appel. Iterated register coalescing. ACM Transactions on Programming Languages and Systems, 18(3):300324, May 1996.

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