T. Sherwood, G. Varghese, and B. Calder. A pipelined memory architecture for high throughput network processors. In 30th International Symposium on Computer Architecture, June 2003. Home/Search Document Details and Download
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T. Sherwood, G. Varghese, and B. Calder, \A pipelined memory architecture for high throughput network processors, " The 30th Annual International Symposium on Computer Architecture (ISCA), pp. 288-299, 2003.
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