Jack W. Davidson and Christopher W. Fraser, Register Allocation and Exhaustive Peephole Optimization, Software -- Practice and Experience 14(9):857-865, September 1984.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....be found in [GH81] Assembler specific optimisations are given in [Han83] Systematic optimisation of assembly code is done by means of peephole optimisers [ASU85, p. 554] Some simple optimisations relevant to the code produced by the G translation process are given in [Jon87, p. 328] Devidson [Dav84] generalises the technique of a simulated stack into a simulated cache. A more general discussion on constructing a peephole optimiser is in [Lam81] The idea for a generic machine description file (and the file name suffix .md was take from the project GNU C compiler [Sta89] The C calling ....

Jack W. Davidson. Register allocation and exhaustive peephole optimization. Software---Practice and Experience, 14(9):857--865, September 1984.

....instrumentation. Some forms of optimization have to be performed on assembly level or machine level code. The oldest is peephole optimization [16] which acts to tidy up code that a compiler has generated; it has since been generalized to include transformations on more machineindependent code [4,5]. Reordering of code to avoid pipeline stalls [6,9,25] is most often done after the code is generated because the pipeline stalls are easier to see then. Other forms of optimization depend on having the entire program at hand all at once. In an environment with separately compiled modules, this ....

Jack W. Davidson and Christopher W. Fraser. Register allocation and exhaustive peephole optimization. Software --- Practice and Experience 14 (9), pp. 857-865, September 1984.

....local scope, machine independent common subexpression elimination. Because all values, including those computed in address calculations, are exposed at the machine level and assigned to pseudo register values that are never re assigned, cacher detects and eliminates all local common subexpressions [DAVI84a]. The combiner phase performs instruction selection by merging adjacent register transfers into singletons and consulting a machine description to determine if some instruction on the target machine has the effect described by the combination. This process transforms the naive code produced by the ....

J. W. Davidson and C. W. Fraser, Register Allocation and Exhaustive Peephole Optimization, Software---Practice and Experience, 14(9), September 1984, 857-865.

....consecutive instructions and replace them, where possible, with an equivalent single instruction. The machine is described by register and memory transfers. Their optimizer is enhanced further using a simple data flow analysis about which resources are accessed or modified by an instruction pair [3], and by automatically generating rules from a test set [4] Tanenbaum s peephole optimizer [14] operates on a stack machine based intermediate code suitable for imperative languages and several machine architec2 tures. A large set of optimizations is given in advance in a table including more ....

Jack W. Davidson and Christoper W. Fraser. Register Allocation and Exhaustive Peephole Optimization. Software -- Practice and Experience, 14(9):857--865, September 1984.

....and instrumentation. Some forms of optimization must be performed on assembly level or machinelevel code. The oldest is peephole optimization [11] which acts to tidy up code that a compiler has generated; it has since been generalized to include transformations on more machine independent code [2,3]. Reordering of code to avoid pipeline stalls [4,7,18] is most often done after the code is generated because the pipeline stalls are easier to see. Other forms of optimization depend on having the entire program at hand all at once. In an environment with separately compiled modules, this may ....

Jack W. Davidson and Christopher W. Fraser. Register allocation and exhaustive peephole optimization. Software--Practice and Experience 14 (9), pp. 857865, September 1984.

....the target program instruction sequence to be edited and, in the case of the prepend and replace operators, an additional instruction sequence with which to edit the target program. Two patch label expressions delimit the target 1 An intermediate code known as register transfer language [12] employed by the GNU C compiler. 73 program instruction sequence to be edited. Each patch expression stores the id of its corresponding record within the patch database, and the instruction sequence within each editing operator is what is eventually emitted to the patch library. Collectively, ....

J. W. Davidson and C. W. Fraser. Register Allocation and Exhaustive Peephole Optimization. Software --- Practice and Experience, 14(9):857--866, September 1984.

....SET SETHI HI( snippet find inst(1) counter addr) SET SETHI LOW( snippet find inst(2) counter addr) SET SETHI LOW( snippet find inst(3) counter addr) return (snippet) FIGURE 2. Low level instrumentation for branch counting on a SPARC processor. 4 level (RTL) instruction description [10]. A crucial difference, however, is that a compiler writer can choose RTL operations with clean semantics and translate constructs to a sequence of operations, while each EEL instruction must capture the semantics of a machine instruction. The remainder of this section presents these abstractions ....

Jack W. Davidson and Christopher W. Fraser. Register Allocation and Exhaustive Peephole Optimization. Software Practice & Experience, 14(9):857--865, September 1994.

....C s int type and Fortran s integer) as 32 bits initially. 7 In summary, our machine is a super set of the MIPS R3000 instruction set architecture with four additional instructions for loading and storing 64 bits of data. The extensions are shown below using RTLs (Register Transfer Lists) [DAV84] and the corresponding assembly language instructions: Register Transfer List Representation Assembly Language r[4] R[r[29] 8] r[5] R[r[29] 12] ld64 4,8( 29) R[r[29] 8] r[4] R[r[29] 12] r[5] st64 4,8( 29) f[0] F[r[29] 16] f[2] F[r[29] 20] ldf64 0,16( 29) ....

....In order to design, implement, and evaluate memory bandwidth code improvements for WBMs, we modified an existing retargetable optimizer to include the memory bandwidth code improvements. The optimizer, called vpo, is a sophisticated, global optimizer that can be used to build optimizing compilers [BEN88, DAV84, DAV84] . Figure 1 contains a schematic showing the overall organization of a C compiler constructed using vpo. Vertical columns represent logical phases which operate serially. Columns that are divided horizontally into rows indicate that the sub phases of the column many be executed in an arbitrary ....

Davidson, J. W. and Fraser, C. W. Register Allocation and Exhaustive Peephole Optimization. Software--Practice and Experience 14(9):857-866 September 1984.

....in such a way that the implementation of the algorithms does not become machine dependent. The LIL representation used is based on RTLs. RTLs have been used successfully to automate machine specific portions of a compiler such as instruction selection [Davi84b] common subexpression elimination [Davi84a], and evaluation order determination [Davi84a] These transformations are all local ones and do not require information beyond that contained in a basic block. This new LIL, called WRTL (rhymes with turtle) contains additional information to support global code improvements such as loop invariant ....

....algorithms does not become machine dependent. The LIL representation used is based on RTLs. RTLs have been used successfully to automate machine specific portions of a compiler such as instruction selection [Davi84b] common subexpression elimination [Davi84a] and evaluation order determination [Davi84a]. These transformations are all local ones and do not require information beyond that contained in a basic block. This new LIL, called WRTL (rhymes with turtle) contains additional information to support global code improvements such as loop invariant code motion, induction variable elimination, ....

Davidson, J. W. and Fraser, C. W., "Register Allocation and Exhaustive Peephole Optimization", Software---Practice and Experience, 14(9), September 1984, pp. 857---866.

No context found.

Jack W. Davidson and Christopher W. Fraser, Register Allocation and Exhaustive Peephole Optimization, Software -- Practice and Experience 14(9):857-865, September 1984.

No context found.

Jack W. Davidson and Christopher W. Fraser. Register allocation and exhaustive peephole optimization. Software--Practice and Experience, 14(9):857--866, September 1984.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC