| Y. Wu. Efficient discovery of regular stride patterns in irregular programs and its use in compiler prefetching. In Programming Language Design and Implementation, pages 210--221, 2002. |
.... of the loads that will cause cache misses at runtime is complex, requiring both knowledge of hardware parameters (cache block size, capacity, and associativity) and sophisticated code analysis (e.g. to determine the volume of other data accessed between references to a particular block) [7, 17, 33, 45]. The compiler also faces the difficult challenge of issuing the prefetches sufficiently early to hide the memory latency, but not so early that useful data are needlessly evicted. To find that point, the compiler must estimate cache miss latencies and run time instruction execution rates [25] ....
Y. Wu. Efficient discovery of regular stride patterns in irregular porgrams and its use in compiler prefetching. In Proceedings of the SIGPLAN 2002.
No context found.
Y. Wu. Efficient discovery of regular stride patterns in irregular programs and its use in compiler prefetching. In Programming Language Design and Implementation, pages 210--221, 2002.
No context found.
Y. Wu. Efficient discovery of regular stride patterns in irregular programs and its use in compiler prefetching. In Proceedings of the SIGPLAN 2002.
No context found.
Y. Wu. Efficient discovery of regular stride patterns in irregular porgrams and its use in compiler prefetching. In Proceedings of the SIGPLAN 2002.
No context found.
Y. Wu, "Efficient discovery of regular stride patterns in irregular programs and its use in compiler prefetching," ACM SIGPLAN Notices, vol. 37, no. 5, pp. 210--221, May 2002, published as part of the proceedings of PLDI'02.
No context found.
Y. Wu, "Efficient discovery of regular stride patterns in irregular programs and its use in compiler prefetching," in Programming Language Design and Implementation, June 2002.
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