D. Kirovski, C. Lee, M. Potkonjak, and W. Mangione-Smith, "Application -driven synthesis of core-based systems," in Int. Conf. ComputerAided Design, Nov. 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....design of retargetable, application specific VLIW processors is developed [2] This framework provides the tools to tradeoff architecture organization and compiler complexity. A hierarchical approach is proposed for the design of systems consisting of processor cores and instruction data caches [3]. A minimal area system that satisfies the performance characteristics of a set of applications is synthesized. In contrast to previous work, our framework permits us to explore a large parameterized processor design space in conjunction with a parameterized memory hierarchy design space. A ....

D. Kirovski, C. Lee, M. Potkonjak, and W. M. MangioneSmith, "Application-driven synthesis of core-based systems," presented at Proc. IEEE Int. Conf. on Computer Aided Design (ICCAD), 1997.

....consumption is proportionally higher, resulting in an interesting design trade off. Higher cache associativity results in significantly higher access time. We use a recently developed compiler strategy which efficiently minimizes the number of cache conflicts that considers directmapped caches [14]. We have experimented with 2 way set associative caches which did not dominate comparable direct mapped caches in a single case. Cache line size was also variable in our experimentations. Its variations corresponded to the following trade off: larger line size results in higher cache miss penalty ....

....voltage supply Figure 5. The system performance and power evaluation and simulation platform. To estimate the system performance and power on the configuration under consideration, we use the system performance and power evaluation and simulation platform based on SHADE and DINEROIII [14, 15]. SHADE is a tracing tool which allows users to define custom trace analyzers and thus collect rich information on runtime events. SHADE currently profiles only SPARC binaries. The executable binary program is dynamically translated into host machine code. The tool also provides a stream of data ....

D. Kirovski, C. Lee, W. Mangione-Smith, and M. Potkonjak. Application-driven synthesis of core-based systems. In IEEE/ACM International Conference on Computer-Aided Design, pages 104--107, 1997.

.... applications into memory so as to reduce power consumption has also been studied [26] 15 A system level memory exploration technique targeting ATM applications is presented in [22] A simulationbased technique for slecting a processor and required instruction and data caches is presented in [13]. The work closest to our own is the work of Panda, Dutt and Nicolau who present techniques for partitioning on chip memory into scratchpad memory and cache [18] The presented algorithm assumes a fixed amount of scratchpad memory and a fixed size cache, identifies critical variables and assigns ....

D. Kirovski, C. Lee, M. Potkonjak, and W. Mangione-Smith. Application-Driven Synthesis of CoreBased Systems. In Proceedings of the International Conference on Computer-Aided Design, pages 104--107, November 1997.

....rate reduces with increase in cache size, the energy consumption does not always reduce. Thus it is important to study the tradeoffs between size, time and energy. The exploration procedure described here for data caches can be extended to instruction caches by merging the method of Kirovski et al. [8] with ours. 2. PERFORMANCE METRICS In this section we describe the three performance metrics of our LEAVE BLANK THE LAST 3.81 cm (1.5 ) OF THE LEFT COLUMN ON THE FIRST PAGE FOR THE COPYRIGHT NOTICE 36 th ACM IEEE Design Automation Conference, June 1999. system, namely, cache size, number ....

D. Kirovski, C. Lee, M. Potkonjak, and W. MangioneSmith, "Application --Driven Synthesis of Core-based Systems", In Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pages 104-107, San Jose, CA, November 1997.

.... each partition contains a fixed number of nodes, node of size cache lines is spread over consecutive partitions, and the sum of weights of edges connecting nodes in different partitions is greater than Since the problem of finding the optimum basic block mapping is computationally intractable [20], we opt to employ a heuristic search to obtain a good solution. Although greedy heuristics seem to have acceptable solution quality versus search run time ratio, experiments show that leastconstraining most constrained heuristics provide significantly better results both in terms of solution ....

D. Kirovski, C. Lee, M. Potkonjak, and W. Mangione-Smith, "Application-driven synthesis of core-based systems," in Proc. Int. Conf. Computer-Aided Design, 1997, pp. 104--107.

....in the research community [30] 40] Panda et al. 42] presented a technique for determining the best data cache size for a given application. Panda et al. 41] presented techniques to minimize data cache conflicts for direct mapped caches by analyzing the array access patterns. Kirovski et al. [26] developed techniques to minimize instruction data cache conflicts for direct mapped caches. The techniques proposed in [26] 30] and [40] 42] are complementary to our approach since they can be applied as a preprocessing step. The techniques proposed in [26] 30] and [40] reduce the cache ....

....a given application. Panda et al. 41] presented techniques to minimize data cache conflicts for direct mapped caches by analyzing the array access patterns. Kirovski et al. 26] developed techniques to minimize instruction data cache conflicts for direct mapped caches. The techniques proposed in [26], 30] and [40] 42] are complementary to our approach since they can be applied as a preprocessing step. The techniques proposed in [26] 30] and [40] reduce the cache conflicts, while those proposed in [41] and [42] reduce the size of the cache or improve the performance of the cache, mainly ....

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D. Kirovski, C. Lee, W. Mangione-Smith, and M. Potkonjak, "Application-driven synthesis of core-based systems," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1997, pp. 104--107.

....embedded systems range from 128B to 32KB. Although larger caches correspond to higher hit rates, their power consumption is proportionally higher, resulting in an interesting design trade o#. Since higher cache associativity results in higher access time, we consider only direct mapped caches [Kir97] We have experimented with 2 way set associative. However, they did not dominate in a single case. Cache line size is also variable in our experiments. Its variations 7 correspond to the following trade o#: larger line size results in higher cache miss penalty delay and higher power consumption ....

....of two passes: the first pass determines the boundaries of basic blocks, while the second pass constructs a CFG by adding control flow information between basic blocks. We collect the frequencies of control transfers through each basic block and information on branch temporal correlation [Kir97b] Table 4 shows a typical CFG generated by the analyzer. The first two columns show the basic block starting and ending address. Branch type (conditional[1] unconditional[2] procedure call[4] or indirect branch target jmpl[3] and the number of possible target addresses appear in the next two ....

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D. Kirovski, C. Lee, M. Potkonjak, and W. Mangione-Smith. Application-driven synthesis of core-based systems. International Conference Computer Aided Design, pp.104-7, 1997.

....is linked to SHADE to control and analyze the generated trace information. The analyzer sources relevant trace information from SHADE and builds a control flow graph (CFG) corresponding to the dynamically executed code. Details about the tracing process and collected data are elaborated in [Kir97]. Once the CFG is obtained, an algorithm is employed to reposition application basic blocks in such a way that instruction cache misses and cache decoder switching activity are minimized. Our experimentation uses a basic block relocation look up table to simulate the relocation of basic blocks in ....

....code locations. In other words, sets of basic blocks mapped to the same cache line are reassigned to, not necessarilly, different cache entries such that the number of transitions in the instruction cache decoder is minimized. The first phase in the relocation strategy is described in detail in [Kir97]. The collected run time information on the execution of the program is used to generate and weight a control flow graph (CFG) Then, the CFG is transformed so that spatially and temporally highly probable execution paths are identified. Once the CFG is transformed, basic blocks are selected for ....

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D. Kirovski, et al. Application-driven synthesis of core-based systems, to appear, ICCAD, pp. 104-107, 1997.

....of shutdown, supply voltage reduction, both shutdown and supply voltage reduction, and dynamically variable voltage approach, respectively. With the shutdown technique, the system will operate at Vdd = 3:3 volts. The TaskA is executed in the interval [0, 5] The TaskB is executed in the interval [5,10]. The processor can be shut down for the interval [10, 20] and then be resumed for the next task. The duty cycle of the processor is 50 , so the average power consumption is 0:5 Watts. With the supply voltage reduction technique, the system will operate at a lower but fixed supply voltage. The ....

....supply voltage reduction, and dynamically variable voltage approach, respectively. With the shutdown technique, the system will operate at Vdd = 3:3 volts. The TaskA is executed in the interval [0, 5] The TaskB is executed in the interval [5,10] The processor can be shut down for the interval [10, 20] and then be resumed for the next task. The duty cycle of the processor is 50 , so the average power consumption is 0:5 Watts. With the supply voltage reduction technique, the system will operate at a lower but fixed supply voltage. The tight deadline on TaskA means that supply voltage can not be ....

[Article contains additional citation context not shown here]

D. Kirovski, C. Lee, W. Mangione-Smith, and M. Potkonjak. Application-driven synthesis of core-based systems. In IEEE/ACM International Conference on Computer-Aided Design, pages 104--107, 1997.

....to drive a system on a chip synthesis experiment. If the resulting systems are functionally different we will know that the suite adds value to the practice of designing embedded systems. The synthesis process adopted here is similar to those currently being pursued in the CAD research community [22, 23]. The goal of this experiment is to evaluate the usefulness of the MediaBench suite, not to present a fundamental new approach to system synthesis. One of the most pressing demands on embedded system designers is to reduce cost, in large part through reducing die size. Because of this concern, we ....

D. Kirovski, C. Lee, W. H. Mangione-Smith, and M. Potkonjak, "Application-Driven Synthesis of Core-Based Systems," Proc. of International Conference on Computer Aided Design, 1997.

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D. Kirovski, C. Lee, M. Potkonjak, and W. Mangione-Smith, "Application -driven synthesis of core-based systems," in Int. Conf. ComputerAided Design, Nov. 1997.

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D. Kirovski, C. Lee, M. Potkonjak, and W. H. Mangione-Smith, "Application-driven synthesis of core-based systems," in Proc. Int. Conf. Computer-Aided Design, Nov. 1997, pp. 104--107.

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D. Kirovski, C. Lee, M. Potkonjak, and W. Mangione-Smith, "Application -driven synthesis of core-based systems," in Int. Conf. ComputerAided Design, Nov. 1997.

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