H. Ural, Formal methods for test sequence generation, Computer Communications Journal, 15(5), pp 311--325, 1992  Home/Search   Document Not in Database   Summary   Related Articles   Check

....Estelle specifications, feasibility constraints related to multiple concurrent timers are also of special concern for specifications in SDL. The conflicting timers problem is a special case of the feasibility problem of test sequences, which is an open research problem for the general case [27] [67]. However, there are two simplifying features of the conflicting timers problem: 1) timer related variables are linear, and (2) the values of time keeping variables implicitly increase with time. Considering these features makes it possible to find an efficient solution to this special case. C.1 ....

H. Ural. Formal methods for test sequence generation. Computer Communications, 15(5):311325, Jun. 1992. 23

....variables [22] Test generation from EFSM models has been an active research area. Sarikaya et al. used the functional program testing approach to generate test sequences from the EFSMs [64] Software data flow testing approaches have been used to generate tests for the communication protocols [70, 71, 72]. Ural applied the all uses [72, 61] criterion, used for testing software written in block structured programming languages, to Estelle [12, 13] specification of protocols. Miller and Paul [54] introduced a method to generate tests for both control and data for EFSM models. Chanson and Zhu [15] ....

....EFSM models has been an active research area. Sarikaya et al. used the functional program testing approach to generate test sequences from the EFSMs [64] Software data flow testing approaches have been used to generate tests for the communication protocols [70, 71, 72] Ural applied the all uses [72, 61] criterion, used for testing software written in block structured programming languages, to Estelle [12, 13] specification of protocols. Miller and Paul [54] introduced a method to generate tests for both control and data for EFSM models. Chanson and Zhu [15] proposed a test generation method ....

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H. Ural. Formal methods for test sequence generation. Computer Communications, 15(5):311-325, Jun. 1992.

....2.5 Related Work Test generation from EFSM models has been an active research area. Sarikaya et al. used the functional program testing approach to generate test sequences from the EFSMs [64] Software data flow testing approaches have been used to generate tests for the communication protocols [71 73]. Ural applied the all uses [73,61] criterion, used for testing software written in block structured programming languages, to Estelle [13,14] specification of protocols. Miller and Paul [55] introduced a method to generate tests for both control and data for EFSM models. Chanson and Zhu [17] ....

....from EFSM models has been an active research area. Sarikaya et al. used the functional program testing approach to generate test sequences from the EFSMs [64] Software data flow testing approaches have been used to generate tests for the communication protocols [71 73] Ural applied the all uses [73,61] criterion, used for testing software written in block structured programming languages, to Estelle [13,14] specification of protocols. Miller and Paul [55] introduced a method to generate tests for both control and data for EFSM models. Chanson and Zhu [17] proposed a test generation method which ....

H. Ural. Formal methods for test sequence generation. Computer Communications, 15(5):311-325, Jun. 1992.

....of heterogeneous devices in a complex communications network, each component of such a network must be tested for conformance against its specification. Automated generation of conformance tests based on the formal descriptions of communication protocols has been an active research area [1] [16] These techniques, using a deterministic finite state machine (FSM) model of a protocol specification, focus on the optimization of the test sequence length. If, however, there exist timing constraints imposed by a protocol s active timers and these constraints are not considered during ....

.... TIMER ON TOP UPDATE REQ TIMER INACTIVE 25,26,30,32,35] ON 30,32,34,35] T[ 7,8,12,13,15,20, 25,30,32,35] T[ 7,8,10,12,13,14, 15,17,19,20,28,29, 30,32,34,35] T[ 2 6,7,8,25,26,32,35] T[ 9,11,16,18,22,27,33] T[ 9,11,16,18,22,27,29,33] T[23] T[23] T[21] T[24] T[31] T[29] T[31] T[31] T[31] T[1] T[21,29] T[24] Figure 1: Extended FSM for Topology Update module of MIL STD 188 220B. a solution for this optimization problem is presented in Section 6. Existence proofs of a polynomial time solution are given in the Appendix. 2 Motivation During testing, traversing each state transition of an ....

H. Ural, "Formal methods for test sequence generation," (Elsevier) Comput. Commun., vol. 15, pp. 311--325, June 1992.

....both e 1 and e 5 contains condition conflict e 1 requires that 1 = 0# and e 5 that 1 = 1#. Both test sequences are therefore infeasible. Test generation for this EFSM is a special case of the feasibility problem of test sequences, which is an open research problem for the general case [26]. However, the model has two simplifying features: 1) timer related variables are linear, and (2) the values of time keeping variables implicitly increase with time. Considering these features makes it possible to find an efficient solution to this special case. The EFSM to FSM conversion ....

H. Ural. Formal methods for test sequence generation. Comput. Commun., 15(5):311--325, June 1992.

....conformance to their specifications has become an integral part of the product development cycle. Without the help of formal methods in protocol testing, the interoperability of devices is questionable. Various methods for automated test generation from protocol specifications have been proposed [1, 4, 5, 13, 15, 16, 17, 18, 20, 22], based on a deterministic finite state machine (FSM) model of the specification. Although existing test generation methods concentrate on optimizing the test sequence length, these methods place no restrictions on the order in which the tests can be applied to an implementation under test (IUT) ....

....on the number of self loop transitions traversed consecutively. OFF BOTHTIMERS ON TOP UPDATE TIMER ON TOP UPDATE REQ TIMER INACTIVE 25,26,30,32,35] ON 30,32,34,35] T[ 7,8,12,13,15,20, 25,30,32,35] T[ 7,8,10,12,13,14, 15,17,19,20,28,29, 30,32,34,35] T[ 2 6,7,8,25,26,32,35] T[ 9,11,16,18,22,27,33] T[ 9,11,16,18,22,27,29,33] T[23] T[23] T[21] T[24] T[31] T[29] T[31] T[31] T[31] T[1] T[21,29] T[24] Figure 1: Extended FSM for Topology Update module of MIL STD 188 220A. In general, the majority of tests defined for an IUT are classified into two categories: valid and inopportune ....

[Article contains additional citation context not shown here]

H. Ural. Formal methods for test sequence generation. (Elsevier) Comput. Commun., 15(5):311--325, 1992.

....a coverage of 95 of the transitions defined in the specification. Keywords: Conformance testing; Embedded testing; Test case generation; Communication protocol specification and testing 1 Introduction In the automated generation of conformance tests based on the formal description of a protocol [1, 4, 15, 19, 20, 28, 32, 33], one significant problem is taking into account a tester s limited controllability on generating inputs to an Implementation Under Test (IUT) 19, 27] This limited control almost always renders certain protocol features untestable. In an embedded testing environment, a composite System Under ....

URAL, H. Formal methods for test sequence generation. (Elsevier) Comput. Commun. 15, 5 (June 1992), 311--325.

....timer tm j expires in transition e 1 ) The solution to the above problem is expected to allow generating low cost tests free of such conflicts. The conflicting timers problem is a special case of the feasibility problem of test sequences, which is an open research problem for the general case [9, 18]. However, there are two simplifying features of the conflicting timers problem: 1) time variables are linear, and (2) time keeping variable values implicitly increase with time. By considering these features, we expect to find an e#cient solution to this special case. 2.1 General approach The ....

....edges and is not disrupted by timeout events during traversal (i.e. contains only feasible transitions) In Section 3, a model will be introduced that allows the generation of test sequences satisfying the above criteria. 2. 2 Related work Conformance test generation is an active research area [1, 3, 9, 11, 14, 17, 18]. The related work on testing systems with timing dependencies focuses on testing the so called Timed Automata (TA) 2, 16] which are a formalism primarily used in system verification. However, there is relatively little work reported in the literature on successful application of timed automata ....

H. Ural. Formal methods for test sequence generation. (Elsevier) Comput. Commun., 15(5):311--325, 1992.

....the methodology allows us to generate tests free of interruptions due to timeouts, and covering more than 95 of the defined transitions in 188 220B s Type 1 Datalink Layer. 1 INTRODUCTION Testing protocol implementations for conformance to their specifications has been an active research area [16] [14] In a testing environment, a tester s control over an Implementation Under Test (IUT) may be limited. This problem is likely to make certain protocol features untestable. In an ideal situation, it should be possible to apply to the IUT every possible input that is defined in the protocol ....

H. Ural. Formal methods for test sequence generation. (Elsevier) Comput. Commun., 15(5):311--325, 1992.

....augmented with an additional reflexive transition. On receipt of a status message the status transition outputs a token unique to its state. The operation checking tour can then be extended with an additional status message state identifier output pairing after each transition. Figure 2. 1 (from [Ura92] shows a FSM with added status transitions those reflexive transitions that take input s. Detecting transfer errors The use of status transitions may not be possible in many implementations, for example, due to strict constraints on the input output interfaces of the system. In these cases, ....

....a new graph with the same vertices as the original machine but whose transitions are augmented with transitions corresponding to the start and end points of the UIO sequences. A minimum cost tour is then calculated that traverses each UIO at least once. Further work by Shen et al. SLD] and Ural [Ura92] describe methods by which UIO sequences can be chosen from a set of possibilities for each state such that the length of the resulting CPT is reduced. Other work [MP91, Hie97a] has exploited the fact that state checking sequences may overlap to produce shorter test sequences. Evaluation of ....

Hasan Ural. Formal methods for test sequence generation. Computer Communications, 15(5):311--325, June 1992.

....200 to over 700. Dr. Uyar performed this research while a Visiting Associate Professor at University of Delaware. 1. Introduction Due to increasing complexity of communication protocols, automated generation of conformance tests based on the formal descriptions has been an active research area [23] [20] One problem that exists in today s conformance testing stems from the limited controllability of an Implementation Under Test (IUT) which almost always renders certain protocol features unrestable. Ideally, testers should be able to generate every possible input that is defined in the ....

H. Ural. Formal methods for test sequence generation. (Elsevier) Cornput. Commun., 15(5):311-325, June 1992.

....the methodology allows us to generate tests free of interruptions due to timeouts, and covering more than 95 of the defined transitions in 188 220B s Type 1 Datalink Layer. 1 Introduction Testing protocol implementations for conformance to their specifications has been an active research area [1] [10] In a testing environment, a tester s control over an Implementation Under Test (IUT) may be limited. This problem is likely to make certain protocol features untestable. In an ideal situation, it should be possible to apply to the IUT every possible input that is defined in the protocol ....

H. Ural, "Formal methods for test sequence generation," Computer Communications, vol. 15, pp. 311--325, Jun 1992.

....a coverage of 95 of the transitions defined in the specification. Keywords: Conformance testing; Embedded testing; Test case generation; Communication protocol specification and testing 1 Introduction In the automated generation of conformance tests based on the formal description of a protocol [1, 5, 16, 20, 21, 29, 33, 34], one significant problem is taking into account a tester s limited controllability on generating inputs to an Implementation Under Test (IUT) 20, 28] This limited control almost always renders certain protocol features untestable. In an embedded testing environment, a composite System Under ....

URAL, H. Formal methods for test sequence generation. Comput. Commun. 15, 5 (June 1992), 311--325.

....between adjacent binary bits. For example, 01100 is a transition tour sequence because it has all four transitions 0 1, 1 0, 1 1 and 0 0 between adjacent bits. The definition of transition tour is consistent with the general definition of transition tours defined for finite state machines in [1 5]. We want to find a function, f(k) that counts the number of distinct length k transition tour sequences. An application of transition tour sequences in testing registers (for data path designs) and memory elements for finite state machines has been shown in [6] Transition tour sequences relate ....

....path designs [6] generally model the behavior of D flip flops or D latches [8] In [6] transition tour sequences were called checking sequences. The change in terminology was motivated by two reasons. First, the use of transitiontour sequence is consistent with earlier definitions in references [1 5]. Second, the term checking sequence is likely to be considered as a synonym for checking experiments. Although it is argued in [6] that checking sequences for D latches (without considering clock signals) are checking experiments; the consideration of clock signal as an explicit input to the ....

Ural, H., "Formal Methods for Test Sequence Generation," Computer Communications, vol. 15, no. 5, p. 311-325, June 1992.

....transitions or transition sequences directly in AutoFocus, which provides a very intuitive and interactive way of system testing. Finally, one can also automatically compute a transition tour covering all or some of the transitions of a certain automaton using established graph algorithms (see [28]) The test sequence determination will then tell if the transition tour is executable, and if so, will give as a result a corresponding I O behavior of the system. Example. Figure 5 (c) shows a computed test sequence for the (graphical) speci cation transition TIMEOUT1 must be red at some step ....

....[20] discusses criteria for the generation of test cases. 1] describes assessment techniques for speci cation based testing. By their very nature, both references are applicable to all methods of generating test sequences. There are several formalizations of testing: for (extended) nite state [28, 23], for algebraic speci cations [7] and for general labeled transition systems [5, 27] MSCs as a language for test case speci cations are described in [9] The focus is on telecommunication. 17, 6] advocate the use of Constraint Logic Programming for software validation for reactive systems. ....

H. Ural. Formal methods for test sequence generation. Computer Communications, 15(5):311-325, June 1992.

....when timer tm j expires in transition e 1 ) The solution to the above problem is expected to allow generating low cost tests free of such con icts. The con icting timers problem is a special case of the feasibility problem of test sequences, which is an open research problem for the general case [9, 18]. However, there are two simplifying features of the con icting timers problem: 1) time variables are linear, and (2) time keeping variable values implicitly increase with time. By considering these features, we expect to nd an ecient solution to this special case. 2.1 GENERAL APPROACH The ....

....and is not disrupted by timeout events during traversal (i.e. contains only feasible transitions) In Section 3. a model will be introduced that allows the generation of test sequences satisfying the above criteria. 3 2. 2 RELATED WORK Conformance test generation is an active research area [1, 3, 9, 11, 14, 17, 18]. The related work on testing systems with timing dependencies focuses on testing the so called Timed Automata (TA) 2, 16] which are a formalism primarily used in system veri cation. However, there is relatively little work reported in the literature on successful application of timed automata ....

H. Ural. Formal methods for test sequence generation. Comput. Commun., 15(5):311-325, June 1992.

....there exist widely accepted types of faults, such as stack at faults. However, in protocol conformance testing, there does not yet exist any such standardized fault model. Much work has been done on fault based testing for finite state models, see for example, SiLe89] BDD91] PeYe92] [Ural92], PBD93] and 3 extended finite state machines (EFSMs) GrPe90] FaPe90] PrGu91] MiPa92] ChZh93] WaLi93] In software testing, the relation between input domains and execution paths has been extensively studied and fault models for the domain boundaries have been used for test suite ....

....test suite. Here we consider only those tests which rely on a reliable reset feature in the implementations under test. The corresponding conditions for the case without reset are somewhat more complicated [Henn64] Hsie71] YPB93] Other methods for test derivation [SiLe88] SiLe89] BoUy91] [Ural92], MiPa93] UrZh93] MCS93] do not guarantee fault coverage in all cases. 3.1. Tests for complete deterministic FSMs Let M S = S, X, Y, s 1 , d, l be a complete reduced deterministic FSM (CDFSM) Let TS be a test suite for the M S . By X a we denote the set of all input sequences ....

H. Ural, "Formal Methods for Test Sequence Generation", Computer Comm., Vol. 15, No. 5, 1992, pp. 311-325.

....of heterogeneous devices in a complex communications network, each component of such a network must be tested for conformance against its specification. Automated generation of conformance tests based on the formal descriptions of communication protocols has been an active research area [1] [16] These techniques, using a deterministic finite state machine (FSM) model of a protocol specification, focus on the optimization of the test sequence length. If, however, there exist timing constraints imposed by a protocol s active timers and these constraints are not considered during ....

.... T[ 7,8,12,13,15,20, 25,26,30,32,35] ON T[ 15,17,19,20,26,28, 30,32,34,35] T[ 7,8,12,13,15,20, 25,30,32,35] T[ 7,8,10,12,13,14, 15,17,19,20,28,29, 30,32,34,35] T[ 2 6,7,8,25,26,32,35] T[ 9,11,16,18,22,27,33] T[ 9,11,16,18,22,27,29,33] T[23] T[23] T[21] T[24] T[31] T[29] T[31] T[31] T[31] T[1] T[21,29] T[24] Fig. 1. Extended FSM for Topology Update module of MIL STD 188 220B. inconclusive verdict or, worse, a wrong verdict (i.e. failing the IUTs even when they meet the specification, or passing non conformant IUTs) Clearly, this is not the goal of testing. Therefore, a properly ....

H. Ural, "Formal methods for test sequence generation," Comput. Commun., vol. 15, pp. 311--325, June 1992. 24

....the methodology allows us to generate tests free of interruptions due to timeouts, and covering more than 95 of the defined transitions in 188 220B s Type 1 Datalink Layer. 1 Introduction Testing protocol implementations for conformance to their specifications has been an active research area [1] [10] In a testing environment, a tester s control over an Implementation Under Test (IUT) may be limited. This problem is likely to make certain protocol features untestable. In an ideal situation, it should be possible to apply to the IUT every possible input that is defined in the protocol ....

H. Ural, "Formal methods for test sequence generation," Computer Communications, vol. 15, pp. 311--325, Jun 1992.

....the methodology allows us to generate tests free of interruptions due to timeouts, and covering more than 95 of the defined transitions in 188 220B s Type 1 Datalink Layer. 1 Introduction Testing protocol implementations for conformance to their specifications has been an active research area [1] [10] In a testing environment, a tester s control over an Implementation Under Test (IUT) may be limited. This problem is likely to make certain protocol features untestable. In an ideal situation, it should be possible to apply to the IUT every possible input that is defined in the protocol ....

H. Ural, "Formal methods for test sequence generation," Computer Communications, vol. 15, pp. 311--325, Jun 1992.

....coverage of 95 of the transitions defined in the specification. Keywords: Conformance testing; Embedded testing; Test case generation; Communication protocol specification and testing 1 Introduction In the automated generation of conformance tests based on the formal description of a protocol [1, 5, 16, 20, 21, 29, 33, 34], one significant problem is taking into account a tester s limited controllability on generating inputs to an Implementation Under Test (IUT) 20, 28] This limited control almost always renders certain protocol features untestable. In an embedded testing environment, a composite System Under ....

URAL, H. Formal methods for test sequence generation. Comput. Commun. 15, 5 (June 1992), 311--325.

....on the automatic generation and validation of test cases. As has been shown, automating test case generation can make testing easier and more effective [JPP 97] Several techniques for automatic test case generation from behavior descriptions like Mealy Machines [Cho78, ADLU91, FvBK 91, Ura92] X Machines [IH98] VDM [DF93] or Z [Sad99, HNS97] have been developed in the past. Recently, these techniques have been applied to current industrial graphical description techniques like ones provided by UML [Gro99] Unfortunately, the new approaches consider only single aspects of UML and ....

H. Ural. Formal methods for test sequence generation. Computer communications, 15(5), June 1992.

....deals with the test of individual software components of reactive systems specified by using EFSMs. While testing based on finite state machines (FSMs) i.e. machines which accept a single input and produce a single output at each transition, has been extensively investigated in the literature [16, 12], issues concerning testing based on EFSMs have not been adequately addressed. The main problem of testing on the basis of EFSMs is the relationship and interaction between function test and trace test. By function test we mean the test of individual functions of the software which are ....

....approach based on FSMs, which relies on the coverage of each transition and the identification of the reached state. Different methods, e.g. Distinguishing Sequence (DS) Unique Input Output (UIO) and the method of characterisation sets (or the W Method) differ in the state identification step [16]. The problem of carrying over the test methods based on FSMs to EFSMs is twofold: On the one hand, a transition in an FSM accepts an input and produces an output. Once it has been tested successfully, it can be regarded as correctly implemented. However, in an EFSM the transitions transform a set ....

H. Ural. Formal methods for test sequence generation. Computer Communications, 15(5):311--325, 1992.

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H. Ural, Formal methods for test sequence generation, Computer Communications Journal, 15(5), pp 311--325, 1992

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