K. S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD thesis, Dept. of Computer Science, University of Calgary, Canada, September 1994. 13  Home/Search   Document Details and Download   Summary   Related Articles   Check

....on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and or a fee. DAC 2002, June 10 14, 2002, New Orleans, Louisiana, USA. Copyright 2002 ACM 1 58113 461 4 02 0006 . 5.00. machines [18] Burst Mode AFSMs [15][21] and Direct mapped AFSMs [6] 14] However, only a few of these approaches are suitable for EDA. The fundamental requirement is that they use standard logic gates. An important additional requirement is that the derived circuits possess easy to determine timing constraints, which can be ....

K. S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD thesis, Department of Computer Science, The University of Calgary, September 1994.

....Newcastle upon Tyne and CVCP. Supported by EPSRC grant No. GR J 52327 Several asynchronous processor designs have been completed. Amongst the most recent ones are AMULET1 from Manchester University [6] an asynchronous microprocessor from Caltech [8] an HP Lab s microprocessor called Mayfly [20], and TITAC from Tokyo Institute of Technology [12] Each of these design groups used their own formalisms during the design process. For example, the microprocessor designed by Alain Martin s group at Caltech used a CSP like language. CCS [10] formalisms were used to verify the specifications and ....

K.S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD thesis, The University of Calgary, September 1994.

....the burst mode specification. The first usage of burst mode state machines can be traced back to a packet routing chip called Postoffice designed by Davis, Stevens, and Coates at HP Laboratories [26] State machines in Postoffice were synthesized by an automatic synthesis tool called MEAT [23] [31]. However, the implementations were not guaranteed hazard free: a verifier was used to detect any hazards, and if they occurred, resynthesis was performed. Nowick and Dill at Stanford later restricted and formalized the specification format used at HP Laboratories (and coined the term ....

K. S. Stevens, Practical Verification and Synthesis of Low Latency Asynchronous Systems, Ph.D. thesis, Dept. of Computer Science, University of Calgary, Canada, Sept. 1994.

....them more vulnerable to intermittent effects, such as noise and glitches occurring on the input lines. Any unspecified input change may start a sequence of internal transitions leading to an erroneous state. Asynchronous interface designs based on a multiplexed bus are prone to such situations [4, 10] to a much greater extent than point to point interconnections used in a ring. The design reported in [12] lacks one important feature: its protocol has not been formally proven correct. It is only believed, on the grounds of simulation results, to be deadlock free and fair (with respect to its ....

K.S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD Thesis, The University of Calgary, Calgary, Alberta, Sept. 1994.

....a manual flow. Automated tool support for these flows was painfully lacking, so we began mentoring development of RT CAD. Early engagement with the Petrify team led to automation of synthesis using relative timing [20] Verification using RT constraints was added to the verification tool Analyze [27] in house. This tool was used to optimize the constraints in a slow, error prone manual loop. Theory automating the verification and RT constraint optimization is under development [25] We encourage researchers to further formalize and develop new CAD for automating RT design. IV. EXAMPLES A. ....

....and gates. 3) Relative Timing Verification: This section introduces the method developed to verify a large, relative timed asynchronous circuit called RAPPID [1] An implementation conforms to a specification when an implementation is an acceptable construction of the specification [16] [27], 34] In this section, implementations can be assumed to be parallel compositions of the untimed behavioral specifications of the gates. Relative timing predicates can be added to implementations and specifications to reduce their concurrency by pruning states in a state graph (SG) that are ....

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K. S. Stevens, "Practical verification and synthesis of low latency asynchronous systems," Ph.D. dissertation, Univ. of Calgary, Calgary, Alta., Canada, 1994.

....key observations were mostly related to methods for asynchronous control circuit optimizations [3] 1) Relative timing assumptions were used to simplify the control circuits thus increasing their performance. 2) Relative timing assumptions were added to the formal verification tool ANALYZE [22]. 3) Pulsed pipeline control simplified the circuit and increased performance. 4) A footed rather than unfooted domino may yield a faster circuit due to relaxed race conditions. Self timed circuits are a potential solution to future design problems like delay variations and clock distribution. ....

K. S. Stevens, "Practical verification and synthesis of low latency asynchronous systems," Ph.D. dissertation, University of Calgary, Calgary, Alberta, Canada, Sept. 1994.

....key observations were mostly related to methods for asynchronous control circuit optimizations [3] 1. Relative timing assumptions were used to simplify the control circuits thus increasing their performance. 2. Relative timing assumptions were added to the formal verification tool ANALYZE [22]. 3. Pulsed pipeline control simplified the circuit and increased performance. 4. Footed rather than unfooted domino may yield a faster circuit due to relaxed race conditions. Self timed circuits are a potential solution to future design problems like delay variations and clock distribution. We ....

Kenneth S. Stevens, Practical Verification and Synthesis of Low Latency Asynchronous Systems, Ph.D. thesis, University of Calgary, Calgary, Alberta, Sept. 1994.

....key observations were mostly related to methods for asynchronous control circuit optimizations [3] ffl Relative timing assumptions were used to simplify the control circuits thus increasing their performance. ffl Relative timing assumptions were added to the formal verification tool ANALYZE [22]. ffl Pulsed pipeline control simplified the circuit and increased performance. ffl Footed rather than unfooted domino may yield a faster circuit due to relaxed race conditions. Self timed circuits are a potential solution to future design problems like delay variations and clock distribution. ....

Kenneth S. Stevens, Practical Verification and Synthesis of Low Latency Asynchronous Systems, Ph.D. thesis, University of Calgary, Calgary, Alberta, September 1994.

....for the time vectors. Starting from the initial states, TLCS decides if the mutually reachable set of states satisfy the TLC relation, and it produces counterexamples when TLC does not hold. 3. TIMED LOGIC CONFORMANCE Based on the bisimulation style Logic Conformance relation l of Stevens [Ste94] we define a timed relation called Timed Logic Conformance LC t for Timed Safety Automata (TSA) based on DLTS semantics. LC t enforces a time interval based relationship between imp actions and spec actions. It also maintains l s partial order relationship between specs and imps. LC t ....

Kenneth S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD thesis, The University of Calgary, Calgary, Alberta Canada, September 1994.

....in the reset function. The combination of state holding and low transition latency of the domino gates made them the best circuit alternative we investigated. A key aspect to the correct operation of the silicon was the verification of these timed circuits. The timing verification tool Analyze [15] was enhanced to support relative timing verification. The verifier was also used to generate a complete set of RT constraints from the critical races in a circuit. These constraints enforce a particular resolution of the races that guarantee correct operation of a circuit. This is shown in ....

....specification. Verification engines can be enhanced to support relative timing by generating a set of RT constraints from these verification failure states. The following two explicit relative timing constraints on the burst mode implementation were generated by an enhanced version of Analyze 1 [15]: RTC4: bz OE a# RTC5: az OE b# Valid sets of RT constraints are not necessarily unique. The following is another set of RT constraints that are less restrictive because they do not require circuit stability: RTC6: bz OE ab# RTC7: az OE ab# 1 Analyze is a bisimulation verifier. Only ....

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K. S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD thesis, University of Calgary, Calgary, Alberta, September 1994.

.... ab Gamma. SPICE simulations or separation analysis can be used to guarantee that this timing requirement on the physical circuit will hold. This circuit will be valid if the delay in the environment producing the input a Gamma is slower than bc Gamma. An RT enhanced version of the verifier [12] was used to check the timing of many of the hand designed timed circuits in RAPPID using this method. 6 Future directions Although significant progress has been reached in automation for RT asynchronous circuits during the RAPPID project, in particular in the area of logic design, we believe ....

Kenneth S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD thesis, University of Calgary, Calgary, Alberta, September 1994.

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K. S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD thesis, Dept. of Computer Science, University of Calgary, Canada, September 1994. 13

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K. S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD thesis, Department of Computer Science, University of Calgary, September 1994.

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Stevens K.S., "Practical Verification and Synthesis of Low Latency Asynchronous Systems," PhD Thesis, The University of Calgary, Calgary, Alberta, Sept.1994.

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