A. Aleta, J. Codina, J. Sanchez, and A. Gonzalez. Graph-partitioning based instruction scheduling for clustered processors. In Proc. of the 34th Annual International Symposium on Microarchitecture, pages 150--159, Dec. 2001. Home/Search Document Details and Download
Summary Related Articles Check |
This paper is cited in the following contexts:
Exploiting Pseudo-schedules to Guide Data.. - Aleta, Codina.. (2002) (2 citations) Self-citation (Aleta Codina Sanchez Gonzalez) (Correct)
No context found.
A. Aleta, J. M. Codina, J. Sanchez, and A. Gonzalez. GraphPartitioning Based Instruction Scheduling for Clustered Processors. In Proc. of 34th Int. Symp. on Microarchitecture, Dec 2001.
Exploiting Pseudo-schedules to Guide Data.. - Aleta, Codina.. (2002) (2 citations) Self-citation (Aleta Codina Sanchez Gonzalez) (Correct)
....applying the above enhancement, if moving a node from one cluster to another overloads the second cluster (i.e. the latter cluster does not have sufficient resources) we look for a node in the second cluster such that moving it to the first cluster re balances the partition. In previous work [1], we proposed graph partitioning algorithms but did not provide approximate schedules to guide partitioning. As a result, the partitioning decisions were made with much less relevant information. In this work, the partitioning algorithms we present have very precise information produced by the ....
....4. Pseudocode for the register pressure estimation. ule. Moreover, the computed pseudo schedule is quite accurate, especially when the partition is balanced and there is enough space to schedule all instructions in the cluster as specified in the partition. We will use the results presented in [1] as our baseline scheme, since they represent a state of the art approach to modulo scheduling loops on a clustered VLIW processor. 3.2. Scheduling the Instructions Once a partition has been computed, each instruction is scheduled in the assigned cluster. This scheduling is a bidirectional ....
[Article contains additional citation context not shown here]
A. Aleta, J. M. Codina, J. Sanchez, and A. Gonzalez. GraphPartitioning Based Instruction Scheduling for Clustered Processors. In Proc. of 34th Int. Symp. on Microarchitecture, Dec 2001.
Compiler-directed Data Partitioning - For Multicluster Processors (Correct)
No context found.
A. Aleta, J. Codina, J. Sanchez, and A. Gonzalez. Graph-partitioning based instruction scheduling for clustered processors. In Proc. of the 34th Annual International Symposium on Microarchitecture, pages 150--159, Dec. 2001.
A Dependency Chain Clustered Microarchitecture - Narayanasamy, Wang, Wang.. (2005) (Correct)
No context found.
Alex Aleta, Josep M. Codina, Jesus Sanchez, and Antonio Gonzalez. Graph-partitioning based instruction scheduling for clustered processors. In Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, pages 150--159. IEEE Computer Society, 2001.
Optimizing Loop Performance for Clustered VLIW Architectures - Qian, Carr, Sweany (2002) (2 citations) (Correct)
No context found.
A. Aleta, J. Codina, J. Sanchez, and A. Gonzalez. Graphpartitioning based instruction scheduling for clustered processors. In Proceedings of the 34th Annual International Symposium on Microarchitecture, pages 150--159, Austin, Texas, Dec. 2001.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC