| J. Um, J. Kim, and T. Kim, "Layout-driven resource sharing in high-level synthesis," in Proc. Int. Conf. Computer-Aided Design, Nov. 2002, pp. 614--618. |
....specific permission and or a fee. ISPD 03, April 6 9, 2003, Monterey, California, USA. Copyright 2003 ACM 1 58113 650 1 03 0004. 5.00. proposed is the distributed register architecture which helps to explicitly separate the long interconnect delays from logic delays. Under this architecture, [11] performed an integrated resource sharing and placement to eliminate the slack time violation due to the interconnect delays. Note that the irregular structure used by both [10] and [11] may cause difficulty for interconnect delay estimation. Regular circuit and layout structures [12] can be ....
....which helps to explicitly separate the long interconnect delays from logic delays. Under this architecture, 11] performed an integrated resource sharing and placement to eliminate the slack time violation due to the interconnect delays. Note that the irregular structure used by both [10] and [11] may cause difficulty for interconnect delay estimation. Regular circuit and layout structures [12] can be employed to avoid this problem. Generally, regular structure facilitates predictability and simplifies the implementation process. In this paper, we present a new synthesis methodology for ....
J. Um, J. Kim and T. Kim, "Layout-Driven Resource Sharing in High-Level Synthesis," in Proceedings of International Conference on Computer Aided Design, pp. 614-618, 2002.
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J. Um, J. Kim, and T. Kim, "Layout-driven resource sharing in high-level synthesis," in Proc. Int. Conf. Computer-Aided Design, Nov. 2002, pp. 614--618.
No context found.
J. Um, J. Kim, and T. Kim, "Layout-driven resource sharing in high-level synthesis," in Proc. Int. Conf. Computer-Aided Design, Nov. 2002, pp. 614--618.
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