G. Vijayan, "Partitioning Logic on Graph Structures to Minimize Routing Cost", IEEE Trans. on CAD, Vol. 9, No. 12, pp. 1326-1334, December 1990. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Software Technologies for Reconfigurable Systems - Hauck, Agarwal (1996) (2 citations) (Correct)
....the partitioning problem on topologies that do not admit a simple routing cost metric, it is necessary to come up with some other method of estimating routing complexity. One method is to model the routing problem as a multicommodity flow problem and use this as part of the partitioning process [Vijayan90] The multicommodity flow problem can estimate the routing complexity on a general graph, meaning that this approach can be used on an arbitrary multi FPGA topology. However, the flow calculation can be very complex, and thus cannot be used in the inner loop of a complex partitioning algorithm. ....
....conditions. However, even with this modification, their algorithm has an exponential worst case complexity. Although the approaches discussed previously can develop reasonably accurate estimates of partitioning quality, they take a significant amount of runtime to complete. The approach in [Vijayan90] has an exponential worst case complexity, and simulated annealing is notoriously slow. An alternative to both of these algorithms is to adapt the standard partitioning algorithms [Alpert95] which ignore interconnection limitations, to partitioning onto a topology. For crossbar topologies, ....
G. Vijayan, "Partitioning Logic on Graph Structures to Minimize Routing Cost", IEEE Trans. on CAD, Vol. 9, No. 12, pp. 1326-1334, December 1990.
Low-Power Architectural Synthesis and the Impact of.. - Mehra, Guerra, Rabaey (1996) (12 citations) (Correct)
....and layout level CAD. A variety of techniques have been used for partitioning at the logic, circuit and layout levels. These include iterative improvement methods such as Kernighan and Lin [19] Fiduccia and Matheyses [20] and simulated annealing [21] bottom up aggregative algorithms such as [22]; top down recursive bi partitioning [23, 24] and spectral partitioning techniques [25 32] We have developed a new behavioral level partitioning method for low power. The basic idea is to derive an ordering of the nodes by using the spectral properties of the graph and then heuristically ....
G. Vijayan, "Partitioning Logic on Graph Structures to Minimize Routing Cost," IEEE Transactions on CAD, Dec. 1990, pp. 1326-1334.
Logic Partition Orderings for Multi-FPGA Systems - Hauck, Borriello (1995) (4 citations) (Correct)
No context found.
G. Vijayan, "Partitioning Logic on Graph Structures to Minimize Routing Cost", IEEE Trans. on CAD, Vol. 9, No. 12, pp. 1326-1334, December 1990.
Logic Partition Orderings for Multi-FPGA Systems - Hauck, Borriello (1995) (4 citations) (Correct)
No context found.
G. Vijayan, "Partitioning Logic on Graph Structures to Minimize Routing Cost", IEEE Transactions on ComputerAided Design, Vol. 9, No. 12, pp. 1326-1334, December 1990.
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