E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units," International Symposium on Low-Power Design, pp. 99-104, 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....large design space. Others attempt to reduce the complexity by looking at a few choices, one control step at a time, thereby potentially excluding good designs [13] Existing work in data characterization, for the most part, has been geared towards illustrating and addressing special cases [9] [12]. There are only a couple models that practically relate data characteristics to transition activity. Others, discussed in [17] 18] are limited by difficulty of use or constraining assumptions. One practical model is the Dual Bit Type (DBT) model [10] 11] which uses probabilistic parameters ....

E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units", in Proc. ISLPED, pp. 99-104, Apr. 1995.

....sharing. Basically they increase the number of similar patterns in resource sharing, hence improving the utilization. Interaction between physical design and resource binding has been addressed in [38] Power dissipation in resource binding has also been actively addressed in [67] 43] [12] and [71] All of them try to reduce the switching activity of of functional units by binding operations which do not result in high switching activity. 2.2 Power Estimation In the past few years, power has become a major optimization objective. This has happent primarily due to the spectacular ....

E. Musoll and J. Cortadella . " High-Level Synthesis Techniques for Reducing the Activity of Functional Units ". In International Symposium on Low Power Electronics and Design, pages 99--104, 1995. 97

.... work on power minimization at the behavioral level has been addressed by considering architectural transformations at the behavioral level [4] Techniques for incorporation of circuit transition activity related cost functions into high level synthesis were presented by Musoll and Cortadella [5], 6] Dasgupta and Karri [7] have reported algorithms for scheduling and binding in order to minimize on chip data bus transitions. Iterative improvement techniques for scheduling and module allocation, based on switched capacitance matrices, were reported by Raghunathan and Jha [8] Martin and ....

E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units," in Int. Symp. Low Power Design, Dana Point, CA, Apr. 1995, pp. 99--104.

....the number of transitions in functional units is increasing the correlation of input data. Therefore, many of the previous work focus on increasing input data correlation by changing operation binding [3, 8] loop pipelining [7] loop interchange, operand reordering, operand sharing, unrolling [5], and guarded evaluation [11] In this paper, we propose yet another technique which we call partially guarded computation. The technique disables a part of a functional unit based on dynamic range of input operands. We divide a functional unit into two parts MSP (Most Significant Part) and ....

E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units," Proceedings of International Symposium on Low Power Design, pp. 99-104, Nov. 1995.

.... unnecessary transitions in the clock signal as well as in the circuit block under consideration [2] Automated synthesis techniques to apply clock gating and maximize its efficiency have been described in [3, 4] Recently, high level synthesis techniques for power management have been proposed [5, 6, 7]. A scheduling algorithm which aims to maximize the idle times for functional units was presented in [6] A controller respecification technique, based on re designing the controller logic to reduce the activity in the components of the datapath was presented in [7] Techniques geared towards ....

....a small overhead in the number of registers. We conclude with an example that demonstrates that spurious switching activity can sometimes be eliminated without increasing the number of registers in the synthesized architecture. Traditional power management techniques, such as those presented in [5, 9], involve the placement of transparent latches at the inputs of a functional unit executing spurious operations. These latches are disabled when the functional unit is idle, thus suppressing spurious operations. This solution has two disadvantages. ffl The signals that detect idle conditions might ....

E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units," in Proc. Int. Symp. Low Power Design, pp. 99--104, Apr. 1995.

....the pre computed values to reduce internal switching activity in the succeeding clock cycle. The above techniques are applicable only to unused idle blocks of logic that are fed by registers, i.e. they are not applicable to circuit blocks embedded within the combinational logic. Operand isolation [7, 8] is a technique that can be used to save power consumption in idle embedded circuit blocks by disabling transitions at their inputs. In operand isolation, transparent latches are inserted at all the inputs of an embedded logic block, and control circuitry is added to detect the idle conditions for ....

.... the register memory constructs in a behavioral description (e.g. variables, arrays) into physical registers memory blocks, with an aim of maximizing opportunities for power management, were presented in [9] The integration of operand isolation into high level synthesis was examined in [8], and found to have potential for significant power savings. A scheduling algorithm to enable power management that attempts to schedule conditional operations before operations that depend on them in order to minimize unnecessary operation executions, was presented in [10] The technique ....

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E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units," in Proc. Int. Symp. Low Power Design, pp. 99--104, Apr. 1995.

....manner. This problem can be avoided if data characteristics are used to efficiently narrow down the design space (i.e. without throwing away good design possibilities. Relationships between data characteristics and ff 0 1 in the datapath were first illustrated for special cases [3] 4] [5]. Then, more general models for relating data characteristics and ff 0 1 began to appear [6] 7] 8] However, these models are targeted for high level power estimation accuracy (under certain assumptions) and do not analyze the causes of ff 0 1 . More general relationships need to be defined ....

....Characteristics As described in Section 2. 1, if nCMD and nIT are not significant, then the average 0 1 transition activity per bit Case Scheduled Order ff 0 1 1 N[0] N[1] N[2] Nominal 2 L[0] L[1] L[2] Low 3 H[0] H[1] H[2] High 4 H[0] H[2] H[4] Low 5 H[1] H[3] H[5], Low 6 H[0] N[0] H[1] N[1] H[2] N[2] Nominal 7 L[0] H[0] L[1] H[1] L[2] H[2] Nominal Table 1. Interesting scheduling options for three data streams allocated to the same 16 bit bus of an N bit node is ff 0 1 = 1 4N fN (1 Gamma ff OS ) 1 3 Gamma nIS ) ff OS ....

E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units", in Proc. ISLPD, Apr. 1995, pp. 99-104.

....and can be achieved without reducing processing speed. This research was supported by the Motorola SABA program and by the Center for Low Power Electronics. In the past, relationships between data characteristics and 1 0 a in the data path have been illustrated for special cases [1] 2][3]. Few general relationships have been defined and modeled to aid in finding low 1 0 a , high level designs. Models that do exist for relating data characteristics and 1 0 a are targeted for high level power estimation accuracy under certain assumptions, not analyzing the causes of 1 0 a [4] 5] ....

Musoll E. and Cortadella J. "High-level Synthesis Techniques for Reducing the Activity of Functional Units". Proc of the Int Symp on Low Power Design, 1995, p 99-104.

....the pre computed values to reduce internal switching activity in the succeeding clock cycle. The above techniques are applicable only to unused idle blocks of logic that are fed by registers, i.e. they are not applicable to circuit blocks embedded within the combinational logic. Operand isolation [8, 9, 10] is a technique that can be used to save power consumption in idle embedded circuit blocks by disabling transitions at their inputs. In operand isolation, transparent latches are inserted at all the inputs of an embedded logic block, and control circuitry is added to detect the idle conditions for ....

.... the register memory constructs in a behavioral description (e.g. variables, arrays) into physical registers memory blocks, with an aim of maximizing opportunities for power management, were presented in [12] The integration of operand isolation into high level synthesis was examined in [10], and found to have potential for significant power savings. A scheduling algorithm to enable power management, that attempts to schedule conditional operations before operations that depend on them in order to minimize unnecessary operation executions, was presented in [13] The technique ....

[Article contains additional citation context not shown here]

E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units," in Proc. Int. Symp. Low Power Design, pp. 99--104, Apr. 1995.

....microprocessor, and Phoenix Technologies NoteBIOS 4.0. Various automated synthesis techniques to apply power management have been proposed, including FSM synthesis for gated clocks [2] multiple clock domains [3] precomputation [4] guarded evaluation [5] operand isolation for functional units [6], and scheduling to enable power management [7] Power management techniques based on clock gating and selectively disabling registers from loading are limited in their scope to reducing power consumption in the clock network, registers, and logic blocks that have registers at their inputs. ....

....are limited in their scope to reducing power consumption in the clock network, registers, and logic blocks that have registers at their inputs. Techniques based on inserting transparent latches to freeze the values at inputs to sub circuits are also applicable to other embedded logic blocks [5, 6]. However, control flow intensive designshave several characteristics which pose challenges to such power management techniques: This work was supported in part by NEC C C Research Labs and in part by NSF under Grant No. MIP 9319269. Permission to make digital hard copy of all or part of this ....

E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units," in Proc. Int. Symp. Low Power Design, pp. 99--104, Apr. 1995.

....This is achieved by scheduling the candidate nodes in control steps as close as possible and binding them to the same resource. The candidate nodes are selected such that there is no change of values in the input operands among consecutive operations of the same functional unit. In addition, in [14], high level transformation techniques such as loop interchange and operand reordering are proposed to reduce the activity of functional units. As a basic control flow element, loop has been one of the major targets of various transformations for optimization of the throughput and the resource ....

....consumption when both operands change simultaneously and a is the ratio P1 P2. If one functional unit is shared by n operation nodes having one common input operand, the power reduction is given by Considering that typical value of a is about 0.65 for a 12bit multiplier and 0. 75 for a 12 bit adder [14], power reductions of 26 and 18 are obtained for n = 4 respectively. The scheduling algorithm proposed by Musoll utilizes this operand sharing technique to obtain power reduction from 5 to 8 over conventional scheduling algorithms. The limitation of the above techniques rises from the fact ....

E. Musoll and J. Cortadella, "High-level synthesis technique for reducing the activity of functional units," in Proc. of Int. Symp. on Low Power Design, pp. 99-104, 1995.

....the objective is to bind operations onto hardware so that the input signal activity is minimized. Raghunathan and Jha [4] propose an assignment scheme to minimize the average number of bit transitions on the signal inputs to hardware units (obtained from simulations) Musoll and Cortadella [5] minimize the bit transitions for constants during scheduling. Consider, for example, the FIR filter of Figure 6. There are four multiplications with constants c 0 , c 1 , c 2 , c 3 which can be scheduled on a single multiplier such that the transition activity at the right input of the ....

....the right input of the multiplier is minimized. For the values of the constants given in the figure, the schedule c 0 c 1 c 2 c 3 c 0 results in 26 transitions for a 12 bit implementation whereas the schedule c 0 c 1 c 3 c 2 c 0 results in 34 transitions. Other methods suggested in [5] for increasing signal transitions include operand sharing (executing operations with common inputs in successive cycles on the same hardware) loop interchange and operand reordering. 9 Chatterjee [6] studied the effect of operand activity on the power consumption of additions and ....

E. Musoll and J. Cortadella, "High-Level Synthesis Techniques for Reducing the Activity of Functional Units," Proceedings of the International Symposium on Low-Power Design, April 1995, pp. 99-104.

....Traditionally, HLS has been applied to obtain small and fast designs, but including power consumption as one of the design parameters or constraints has rarely been addressed. Preliminary studies in the HLS steps of scheduling and resource binding [9] targeting at low power reported in [14] have guided the algorithms presented in this paper. The main target for reducing power consumption is the set of functional units (adders, multipliers) because its power consumption accounts for a large fraction of the overall data path power budget. The algorithms attempt to reduce the activity ....

....of the overall data path power budget. The algorithms attempt to reduce the activity of the functional units by minimizing the switching activity of their input operands. Models derived from switch level simulations of the main data path components (functional, interconnection and storage units) [14] will be used to estimate the power reduction achieved with the algorithms. The paper is organized as follows: in Section 2, previous work on low power circuits with special insight in high level techniques is briefly presented. Section 3 discusses how the functional units consume power in ....

[Article contains additional citation context not shown here]

E. Musoll and J. Cortadella. High-level synthesis techniques for reducing the activity of functional units. In Int. Symp. on Low Power Design, pages 99--104, Apr. 1995.

No context found.

E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units," International Symposium on Low-Power Design, pp. 99-104, 1995.

No context found.

E. Musoll, J. Cortadella, "High-Level Synthesis Techniques for Reducing the Activity of Functional Units," ISLPD-95: 18 pp. 99-104, Dana Point, CA, April 1995.

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Enric Musoll and Jordi Cortadella. High-level Synthesis Techniques for Reducing the Activity of Functional Units. In International Symposium on Low-Power Design, pages 99--104, April 1995.

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E. Musoll and J. Cortadella. High-Level Synthesis Techniques for Reducing the Activity of Functional Units. In Proceedings of the International Symposium on Low Power Design, pages 99--104, April 1995.

No context found.

E. Mussol and J. Cortadella. High-Level Synthesis Techniques for Reducing the Activity of Functional Units. In International Symposium on Low Power Design, pages 99-- 104, April 1995.

No context found.

E. Mussoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units," in Proc. Int. Symp. Low Power Design, Apr. 1995, pp. 99--104.

No context found.

E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units," in Proc. ISLPED, Apr. 1995, pp. 99--104.

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Musoll, E., Cortadella, J., "High-level synthesis techniques for reducing the activity of functional units", ISLPD'95.

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