A. Raghunathan and N. K. Jha, "Behavioral synthesis for low power," Proceedings of International Conference on Computer Design, pp. 318-322, Oct. 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....reduction through activity reduction is a substantial barrier to this technique s acceptance. Existing power reduction techniques that take switching activity into account focus on generating an entire low power data path (functional units, registers, interconnect, buses, etc. for a given CDFG [4], 5] 6] While these techniques are very powerful, the CDFG based techniques are not directly applicable to large systems because of their size and complexity. To aid designers in exploiting switching activity reduction opportunities, this paper first introduces a novel activity model based on ....

....With such a tool, a large design space can be rapidly narrowed down to a few good designs. Existing high level design techniques that consciously try to reduce transition activity do not consider data characteristics. The most basic ones simulate all possible scheduling and allocation choices [4], 16] Thus, these methods are too computationally expensive for narrowing down a typical large design space. Others attempt to reduce the complexity by looking at a few choices, one control step at a time, thereby potentially excluding good designs [13] Existing work in data characterization, ....

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A. Raghunathan and N. Jha, "Behavioral synthesis for low power", in Proc. ICCD, pp. 318-322, Oct. 1994. 31

....this task is a substantial barrier to this power reduction technique s acceptance. Existing methods that take switching activity into account, generate an entire low power data path (functional units, registers, interconnect, buses, etc. for a given control and data flow graph (CDFG) [3] [5] However, a more global approach is needed that first identifies where data characteristics have the Manuscript received July 8, 1999; revised March 2001. This work was supported in part by a Motorola SABA grant and in part by the National Science Foundation (NSF) SIUCRC Center for Low Power ....

....to activity such that the causes of activity can be well understood with little effort. Existing high level design techniques that consciously try to reduce transition activity do not consider data characteristics. The most basic ones simulate all possible scheduling and allocation choices [3] and [9] Thus, these methods are too computationally expensive for narrowing down a typical large design space. Others attempt to reduce the complexity by looking at a few choices, one control step at a time, thereby potentially excluding good designs [10] 11] Existing work in data ....

A. Raghunathan and N. Jha, "Behavioral synthesis for low power," in Proc. ICCD, Oct. 1994, pp. 318--322.

....phase of high level synthesis functional units are selected to perform each operation in CDFG. Various researchers have addresses the problem of minimizing power power dissipation during module allocation and binding. We will discuss few algorithms here in this section. Raghunathan and Jha [8] are the first researchers to purpose the allocation method for low power. The method is based on iterative improvement of some initial solution. The authors assume random input in a structurally pipelined design. The method can also handle non random input sequences. The method is implemented in ....

A.Raghunathan and N.K.Jha, "Behavioral Synthesis for Low Power", Proc. of Intl. Conf. on Comp. Design (ICCD), 1994, pp.318-322.

....With the increasing demand for low power circuits, it has become necessary to modify the three phases of the behavioral synthesis process to minimize the power dissipation. A number of researches have addressed the problem of minimizing power dissipation during module allocation and binding [RaJh94], scheduling, register allocation and binding [RaJh94] ChPe95a] and by trading off area for power through pipelining or parallelization combined with voltage scaling [GoOr94] ChPo92] The work of [ChPe95a] describes a single commodity network flow solution for the register assignment in a ....

....it has become necessary to modify the three phases of the behavioral synthesis process to minimize the power dissipation. A number of researches have addressed the problem of minimizing power dissipation during module allocation and binding [RaJh94] scheduling, register allocation and binding [RaJh94][ChPe95a] and by trading off area for power through pipelining or parallelization combined with voltage scaling [GoOr94] ChPo92] The work of [ChPe95a] describes a single commodity network flow solution for the register assignment in a non pipelined data path. Of particular relevance to the ....

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A. Raghunathan and N. Jha, "Behavioral Synthesis for Low Power", In Proc. Int'l Conf. on Computer Design 1994.

....X and Y. The switching activity of R depends on the correlations between these two variables X and Y. Hence, the power dissipation depends on the register binding as well. These observations form the basis for power optimization during module and register allocation and binding in [14] 13] [56] and [57] In [53] an exact (graph theoretic) algorithm for minimizing the system power through variable voltage scheduling is presented. The idea is establish a supply voltage level for each of the operations in a data flow graph, thereby fixing the latency of that operation, such that the ....

A. Raghunathan and N. K. Jha. " Behavioral synthesis for low power. " In Proceedings of the IEEE International Conference on Computer Design, pages 318-322, October 1994.

....computing and communication products. Chandrakasan et al. Cha92] demonstrated the effectiveness of transformations by showing an order of magnitude reduction in several DSP computationally intensive examples using simulated annealingbased transformational script. More recently Raghunathan and Jha [Rag94] also proposed methods for power minimization which explore trade offs between voltage scaling, throughput, and power. 2.0 Unfolding Driven Voltage Throughput Trade Off Unfolding together with block processing or with look ahead has been shown by various researchers [Par89] to be effective in ....

A. Raghunathan, N.K. Jha, "Behavioral Synthesis for Low Power", International Conference of Computer Design, pp. 318-322, 1994.

....design of low power systems across all level of design abstraction. Chandrakasan et al. 3] showed significant power optimization by using transformations on many computation intensive DSP applications. Methods to explore trade offs between voltage scaling, throughput, and power are reported in [11, 27]. A power reduction scheme targeted at fully hardwired design by minimizing switching activities is presented in [6] Many power minimization techniques targeted at programmable platforms have been introduced [4, 30] We adopt a methodology of system synthesis combining the key paradigms of ....

A. Raghunathan and N. Jha. Behavioral synthesis for low power. In International Conference on Computer Design, pages 318--322, 1994.

....Approach Research in computer aided design techniques for mixed hardware software systems has begun to focus on reducing the power consumption of the systems being produced. Attention has been focused on reducing transition counts in the logic hardware using behavioral synthesis techniques [Rag94][Meh96] reducing memory accesses [Cat97] code generation [Tiw94] Sri96] and shutting down unused parts of a system [Mon96] Our goal is to examine power tradeoffs that can be made in the exploration of the design space. Consider the design of a 4 tap finite impulse response (FIR) filter. The ....

A. Raghunathan and N.K. Jha, "Behavioral Synthesis for Low Power," Proc. of ICCD `94, pp. 318-322, October 1994.

....operations to minimize switching activity at module inputs, as mentioned in the preceding paragraph. The same reasoning obviously applies to the assignment of values to registers. Several approaches have been presented in literature to incorporate switching activity information during binding (Raghunathan and Jha, 1994; Chang and Pedram, 1995) Behavioral synthesis also impacts power consumption by the choice of functional units on which operations are implemented (resource selection) On behavioral level, the power consumption of di erent implementation alternatives can be estimated as a function of the input ....

Raghunathan, A. and Jha, N. K., Behavioral Synthesis for Low Power, in Proceedings of the IEEE International Conference on Computer Design, pp. 318-322, 1994.

....reduction is at the highest levels (behavioral and algorithmic) Chandrakasan et al. 1992] demonstrated the effectiveness of transformations by showing an order of magnitude reduction in several DSP computationally intensive examples using a simulated annealing based transformational script. Raghunathan and Jha [1994] and Goodby et al. 1994] also proposed methods for power minimization which explore trade offs between Delta 6 voltage scaling, throughput, and power. Chatterjee and Roy [1994] targeted power reduction in fully hardwired designs by minimizing the switching activity. Chandrakasan et al. 1994] ....

Raghunathan, A. and Jha, N. 1994. Behavioral synthesis for low power. In International Conference on Computer Design (1994). 318--322.

....like PowerPC, Alpha and Pentium are no exceptions to this problem and hence a drive to investigate into power estimation tech2 niques and low power methodologies. Thus, there have been major efforts [63] to reduce the power consumption, at all levels of abstraction in the design flow[40, 37, 38, 71, 90, 69, 91]. In order to do so, accurate power estimation techniques are desired. At the lower levels of abstraction, although accurate power estimation is possible, it is very time consuming. Thus, recently focus has been shifting to the higher levels of abstraction Register Transfer (RT) level and above ....

....of analytical and stochastic methods. Based on this, a design space exploration tool is presented which is used to examine the effect of different design steps such as transformations and algorithms. These techniques have also been implemented in HYPER synthesis environment [68] Anand et al. [71] present a behavioral synthesis system known as Genesis, for synthesizing low power datapath intensive CMOS circuits. During the allocation phase, 1) the physical capacitance is reduced by minimizing the number of functional modules, registers and multiplexors; and (2) the transaction activity ....

Anand Raghunathan and Niraj K. Jha, "Behavioral Synthesis for Low Power", Proceedings of ICCD, 1994.

....of analytical and stochastic methods. Based on this, a design space exploration tool is presented which is used to examine the effect of different design steps such as transformations and algorithms. These techniques have also been implemented in HYPER synthesis environment [10] Anand et al. [14] present a behavioral synthesis system known as Genesis, for synthesizing low power datapath intensive CMOS circuits. During the allocation phase, 1) the physical capacitance is reduced by minimizing the number of functional modules, registers and multiplexors; and (2) the transaction activity ....

Anand Raghunathan and Niraj K. Jha, "Behavioral Synthesis for Low Power", Proceedings of ICCD, 1994.

....for the system primary inputs. Unfortunately, in some cases, serial allocation may result in suboptimal solutions, i.e. designs using more interconnections than required. It may then be convenient to perform the three operations concurrently (simultaneous allocation) The technique of [65], proposed by Raghunathan and Jha and described next, considers data dominated designs and targets a combined minimization of the total circuit capacitance and the switching activities at the inputs of the registers and the functional modules. The first objective is reached by limiting the total ....

A. Raghunathan and N. K. Jha, "Behavioral synthesis for low power," in Proc. ICCD-94: IEEE Int. Conf. Computer Design, Cambridge, MA, Oct. 1994, pp. 318--322.

....analysis since it is very much dependent on the data input to the system; it is also quite hard to capture the unwanted switching. There are in general two different approaches to switching estimation: calculation based and simulation based [7] 13] In the calculation based switching estimator [5], the switching is computed only analysing the structure of the design and using the switching probabilities of the input signals. The switching probabilities are propagated trough the whole design using some specific transfer function for each component module; the whole process is quite similar ....

....errors introduced by the calculations. The work presented in this report focuses on a Power Estimator using simulation to compute switching. The simulator works at register transfer level (RTL) using Extended Timed Petri Nets (ETPN) 4.Related Work A. Ragunathan and N. K. Jha presented in [5] a framework for low power design called Genesis LP behavioral synthesis system, working on control data flow graphs (CDFG) Their approach to power reduction is the reduction of capacitance and switching activity during allocation, sharing and binding of the resources. Circuit capacitance is ....

A. Raghunathan, N. K. Jha, "Behavioral Synthesis for Low Power," Proceedings of ICCD 1994.

....of interaction of all the above methods and develop interface specifications for an interactive power optimization framework. 3.0 Phase I Accomplishments 3. 1 Technical Approach The technical approach of the Phase I research was to enhance low power optimization methodology developed at Princeton [RaJ94, RaJ95a] and provide VHDL interfaces by integrating Princeton s algorithmic core with ASC s FRITS VHDL object oriented framework. According to the plan, Princeton primarily took charge of algorithm development, while ASC attended to VHDL processing aspects. A complete tool flow of a developed prototype, ....

....is based on obtaining a lower bound on the switched capacitance for the current supply voltage. A module selection is performed by mapping each operation in the CDFG to the functional unit template that has the lowest switched capacitance which is determined using switched capacitance matrices [RaJ94]. A parallel architecture is then chosen to implement the data path. A parallel architecture is typically close to the lowest switched capacitance architecture due to the high temporal signal correlation typical of the digital signal and image processing 8 ASC SBIR Phase I Final Report ....

A. Raghunathan and N. K. Jha, "Behavioral Synthesis for Low Power," in Proc. Int. Conf. Computer Design, Cambridge, Oct. 1994.

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A. Raghunathan and N. K. Jha, "Behavioral synthesis for low power," Proceedings of International Conference on Computer Design, pp. 318-322, Oct. 1994.

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A. Raghunathan and N. K. Jha, "Behavioral synthesis for low power," in Proc Int. Conf. Computer Design, pages 318-322, Oct. 1994.

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A. Raghunathan, N. K. Jha, "Behavioral Synthesis for Low Power," ICCD-94: IEEE International Conference on Computer Design, pp. 318-322, Cambridge, MA, October 1994.

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A. Raghunathan, N. K. Jha, "Behavioral Synthesis for Low Power," IEEE ICCD-94, pp. 318-322, Cambridge, MA, Oct. 1994.

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A. Raghunathan and N. Jha. Behavioral synthesis for low power. In Proceedings of the International Conference on Computer Design, pages 318--322, October 1994.

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A. Raghunathan and N. Jha. Behavioral Synthesis for Low Power. In Proc. of the ICCD, pages 318--322, October 1994.

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A. Raghunathan and N. K. Jha. " Behavioral synthesis for low power. " In Proceedings of the IEEE International Conference on Computer Design, pages 318-322, November 1994.

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A. Raghunathan and N. Jha. Behavioral Synthesis for Low Power. In Proceedings of the International Conference on Computer Design, pages 318--322, October 1994.

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A. Raghunathan and N. Jha, "Behavioral Synthesis for Low Power," in Proceedings of the International Conference on Computer Design, 1994, pp. 318--322.

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Raghunathan, A., Jha, N.K., "Behavioral Synthesis for Low Power", Proceedings of ICCD, 1994.

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