W. Tang, A. Veidenbaum and R. Gupta. Architectural Adaptation for Power and Performance. In ACM International Conference on Supercomputing (ICS), 145-154, 1999. Home/Search Document Details and Download
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Adaptive Online Cache Reconfiguration for Low Power Systems - Nacul, Givargis (2003) (Correct)
....have shown that the best cache configuration depends heavily on the particular running task. Likewise, Zhang et al. #[14] analysis shows that having a dynamically configurable line size architecture can have a significant (up to 50 ) energy saving potential in embedded systems. Tang et al. #[15] have proposed an architectural scheme for dynamic cache line sizing. Their approach is to introduce a hardware unit along with a memory and cache protocol for fine grained tuning of the line size. In contrast, our approach is a software technique that allows the OS to take charge of cache ....
W. Tang, A. Veidenbaum and R. Gupta. Architectural Adaptation for Power and Performance. Proceedings of the International Conference on Supercomputing, pp 145-154, 1999.
Partitioned Cache Architecture as a Side-Channel Defence Mechanism - Page (2005) (1 citation) (Correct)
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W. Tang, A. Veidenbaum and R. Gupta. Architectural Adaptation for Power and Performance. In ACM International Conference on Supercomputing (ICS), 145-154, 1999.
An Analytical Model for Energy Minimization - Claude Tadonki And (2003) (Correct)
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W. Tang, A. V. Veidenbaum, and R. Gupta. Architectural Adaptation for Power and Performance. In , International Conference on ASIC, 2001 .
Dynamic Voltage and Cache Reconfiguration for Low - Nacul, Givargis (2003) (Correct)
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W. Tang, A. Veidenbaum and R. Gupta. Architectural Adaptation for Power and Performance. Proceedings of the International Conference on Supercomputing, pp 145-154, 1999.
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