A. Jain, "Formal Hardware Verification by Symbolic Trajectory Evaluation," Ph.D. Thesis, Electrical and Computer Engineering Department, Carnegie Mellon University, August 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....was based on a marked string formalism, which allowed expression of properties using Boolean operations and a Next Step operator, similar to the AX operator in CTL model checking. Seger [ extended this formalism to account for self looping in the specification state machine, and Jain [17] added support for branching behavior. STE has been heavily utilized in research, and by internal CAD groups at large industrial microprocessor development centers. Pandey focused on using STE to verify memory arrays[ and has applied this work extensively at IBM. 1.4.3 Gate Level Symbolic ....

A. Jain. Formal Hardware Verification by Symbolic Trajectory Evaluation. PhD thesis, Carnegie Mellon University, May 1997.

....Simulation using trajectory evaluation that his FSM method is more focused on finding errors internal to a design, whereas our method is better for finding errors between the interfaces of a design. 3 Our Research Our method uses the principles and techniques of Symbolic Trajectory Evaluation [7] to intelligently pick simulation patterns. In our method the user provides the high level behavior of the system as a set of abstract assertions, where each assertion defines the effect of an operation on the user visible state. An implementation mapping relates each abstract assertion to a set ....

.... that the circuit correctly performs a bitwise or under any number of wait cycles and all possible arrival orders, therefore these implementation specific details and abstract specification are captured by a trajectory graph (Figure 4) The details of trajectory graph generation can be found in [7], and more details on the bitwise or example can be found in [2] Now that the trajectory graph is formed, the process of choosing simulation patterns begins. 7 ALU Register File Subsystem Avalid Bvalid Adata Bdata Tdata Figure 2: Example: Bitwise OR Operation Avalid Adata Bvalid ....

Alok Jain. Formal hardware verification by symbolic trajectory evaluation, July 1997.

....model of circuits used by STE is an abstract interpretation of the ordinary boolean model via a Galois connection. We hope that our exposition will make STE, especially its extended form, less mysterious. 1 Introduction In BDD based formal verification, symbolic trajectory evaluation (STE) [10, 6] is the main alternative to symbolic model checking (SMC) 3] Compared with SMC, STE has the advantage that it can be applied to very large circuits directly, without the need to abstract the circuits before verification. This is made possible by a pleasant property of STE: the number of BDD ....

....the circuit for each assertion, as one often has to do when doing SMC. On the other hand, what STE can verify is more restricted than what SMC can. In its basic form [10] STE can only verify assertions over bounded intervals of time, possibly iterated by non nested loops. But in its extended form [6] 1 , STE can verify assertions expressed as arbitrary state transition graphs, thus enabling STE to verify any safety properties. As far as we know, STE has not been generalized to reason about liveness properties. Unfortunately, STE seems to be much less well known than SMC, certainly less ....

[Article contains additional citation context not shown here]

Alok Jain, "Formal Hardware Verification by Symbolic Trajectory Evaluation", Ph.D. Dissertation supervised by Randal E. Bryant, Carnegie-Mellon University, July 1997.

....specification circuits. Essential to this is the EMM s property to dynamically introduce identical initial state to two simulation sequences [4] In replacing these blocks, we assume that their actual implementations have been verified separately. For example, symbolic trajectory evaluation [16][11] has been combined with symmetry reductions [14] to enable the verification of very large memory arrays at the transistor level. An efficient representation of word level functions has enabled the verification of complex functional units like floating point multipliers [7] Additionally, we ....

A. Jain, "Formal Hardware Verification by Symbolic Trajectory Evaluation," Ph.D. thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, August 1997.

....EMMs. It is also possible to traverse the commutative diagram with another sequence of circuit and memory swaps, i.e. to exercise first the specification side of the diagram. 8. Experimental Results We implemented all the correspondence checking routines, presented in this paper, within a tool [9] that supports the STE technique. Although correspondence checking and STE are two different forms of verification, as noted in Section 1, they have in common the use of a symbolic simulator and the EMM. This allows them to be applied on the same circuit descriptions, which can be in either ....

A. Jain, "Formal Hardware Verification by Symbolic Trajectory Evaluation," Ph.D. thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, August 1997.

....pattern that involves far fewer variables than would be required for a complete binary symbolic simulation. In addition to validation, symbolic ternary simulation has proven to be very powerful for formal verification, as demonstrated by the Symbolic Trajectory Evaluation (STE) technique [12][7]. Furthermore, symbolic ternary simulation can be combined with different delay models. This has been achieved by Seger and Bryant [11] by assuming that gates have zero delays and are connected in series with delay boxes that model inertial delay bounded by a minimum and a maximum value. However, ....

A. Jain, "Formal Hardware Verification by Symbolic Trajectory Evaluation," Ph.D. thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, August 1997.

....our experiments found that the two sequences of traversing the commutative diagram perform comparably in terms of CPU time and memory for our simple circuit presented next. 7. Experimental Results We implemented all the correspondence checking routines, presented in this paper, within a tool [7] that supports the STE technique. Although correspondence checking and STE are two different forms of verification, as noted in Section 1, they have in common the use of a symbolic simulator and the EMM. This allows them to be applied on the same circuit descriptions, which can be in both ....

....input was false) the control signal of the multiplexor is set so as to select the data output of the Hold register. Hence, data forwarding takes effect. For a more detailed description of the circuit (however without a Nop u i = 12 input) and its verification by STE, the reader is referred to [7] for the case of transistor level memory elements, and to [13] for the case of EMM replaced memory elements. For all of the experiments, the dual ported register file was removed from the circuit and replaced with an EMM. The software interface ensures that: 1) a Read operation takes place ....

[Article contains additional citation context not shown here]

A. Jain, "Formal Hardware Verification by Symbolic Trajectory Evaluation," Ph.D. thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, August 1997.

....it with the present one at the Addr input. In case of equality, the control signal of the multiplexor is set so as to select the output of the Hold register. Hence, data forwarding takes effect. For a more detailed description of the circuit and its specifications, the reader is referred to [7][11] For the experiments with the EMM, the dual ported register file is removed from the circuit. The software interface ensures that a Read operation takes place relative to phi1 and a Write operation takes place relative to phi2, according to the register file connections shown in Fig. 8. b) ....

A. Jain, "Formal Hardware Verification by Symbolic Trajectory Evaluation," Ph.D. thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, August 1997.

No context found.

A. Jain, "Formal Hardware Verification by Symbolic Trajectory Evaluation," Ph.D. Thesis, Electrical and Computer Engineering Department, Carnegie Mellon University, August 1997.

No context found.

A. Jain, "Formal Hardware Verification by Symbolic Trajectory Evaluation, " Ph.D. Thesis, Department of Electrical and Computer Engineering, Carnegie Mellon University, August 1997.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC