| M. R. Greenstreet and T. Ono-Tesfaye. Verifying a self-timed divider. In Proceedings of the 1999. |
....inputs that could evoke failures of the metastability filter. We hope that a more convincing verification of the circuit dynamics could be carried out along the lines described in [17] Although this currently does not seem feasible, we are working on developing tools to perform such verification [6, 7]. 3 Performance using model parameters provided by the Canadian Microelectronics Corporation for their 0:8 service. Our simulations are based on schematic level design; thus, layout parasitics are not modeled. We normalize our measurements using a typical gate delay. For this purpose, we ....
M. R. Greenstreet and T. Ono-Tesfaye. Verifying a self-timed divider. In Proceedings of the 1999.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC