A. C. J. Fox. An algebraic framework for modelling and verifying microprocessors using HOL. TR 512, University of Cambridge, 2001. Home/Search Document Details and Download
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Formalizing Java's Two's-Complement Integral Type in Isabelle/HOL - Rauch, Wolff (2003) (Correct)
....a mixture of all four operations, can only be proven up to a length of 9 bits, even with leading edge technology WLDD packages . Amazingly, formalized theories of the two s complement number have only been considered recently; i.e. Fox formalized 32 bit words and the ARM processor for HOL [9], and Bondyfalat developed a (quite rudimentary) bit words theory with division in the AOC project [6] In the context of Java and the JLS, Jacobs [16] presented a fragment of the theory of integral types. This work (like ours) applies to Java Card as well since the models of the four smaller ....
A. C. J. Fox. An algebraic framework for modelling and verifying microprocessors using HOL. TR 512, University of Cambridge, 2001.
Formal verification of the ARM6 micro-architecture - Fox (2002) (2 citations) Self-citation (Fox) (Correct)
....attempt described here. Nevertheless, the verification is substantial and there is scope for carrying out additional more complete verifications in future. The approach used for the formal verification is based on work done at Swansea [17, 16, 14, 11] which has been formalised in hol at Cambridge [12]. This approach provides a general and structured framework for carrying out processor verifications. However, before now only small scale (toy) case studies have been considered. This project aimed to apply these methods to a commercial processor design and, in doing so, assess the suitability of ....
....has been studied, using hol, by Tahar and Kumar [34, 30, 35] All the above used mechanized proof tools. 3 The Formal Verification of Processor Designs This section outlines the approach used in the formal verification of the arm6. A detailed account of this algebraic framework can be found in [12]. 3.1 Approach This section formalises, in an abstract setting, a definition of correctness. This definition can be applied to the formal verification of pipelined microprocessor designs (such as the arm6) The approach is based on comparing two models: 1. The processor s micro architecture ....
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Anthony C. J. Fox. An algebraic framework for modelling and verifying microprocessors using hol. Technical Report 512, University of Cambridge, Computer Laboratory, April 2001.
A HOL specification of the ARM instruction set architecture - Fox (2001) Self-citation (Fox) (Correct)
....how the specification may be used to simulate the execution of arm machine code. 2 Methodology This section outlines the approach used to model the arm architecture. A more extensive account of this methodology, in the context of microprocessor specification and verification, may be found in [3]. 2.1 State Functions and Iterated Maps The arm architecture is modelled as a finite state machine and is given an operational semantics. The set of all possible machine states, as perceived by the programmer, is called the state space and this is defined in Section 3.1. The system is modelled by ....
Anthony C. J. Fox. An algebraic framework for modelling and verifying microprocessors using hol. Technical Report 512, University of Cambridge, Computer Laboratory, April 2001.
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