Z. Lu. Refinement of a system specification for a digital equalizer into HW and SW implementations. Master's thesis, Department of Microelectronics and Information Technology, Royal Institute of Technology, December 2001. IMIT/2001-18. Home/Search Document Details and Download
Summary Related Articles |
This paper is cited in the following contexts:
System Modeling and Design Refinement in ForSyDe - Sander (2003) (Correct)
....An example for such a component is a microprocessor core that can be placed on a system on a chip. 129 To date ForSyDe defines a mapping to hardware (VHDL) and sequential software (C C ) This thesis focuses on the mapping to hardware, while the mapping to software is described in [73] and [72]. At this state ForSyDe does not support hardware software partitioning. This task is left to the designer. 6.2 Mapping of the implementation model to VHDL ForSyDe defines mapping rules from the implementation model to VHDL. In order to get a good implementation, the implementation model must ....
Z. Lu. Refinement of a system specification for a digital equalizer into HW and SW implementations. Master's thesis, Department of Microelectronics and Information Technology, Royal Institute of Technology, December 2001. IMIT/2001-18.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC